DJLXT386LE.B2 S E001 Intel, DJLXT386LE.B2 S E001 Datasheet - Page 40

• Manufacturer Part Number: DJLXT386LE.B2 S E001
• Manufacturer: Intel

Specifications of DJLXT386LE.B2 S E001

• Lead Free Status / RoHS Status: Not Compliant

LXT386 — QUAD T1/E1/J1 Transceiver
3.12.1
3.12.2
40
The Motorola interface is selected by asserting the MOT/INTL pin Low. In non-multiplexed mode
the falling edge of DS is used to latch the address information on the address bus. In multiplexed
operation the address on the multiplexed address data bus is latched into the device with the falling
edge of AS. In non-multiplexed mode, AS should be pulled High.
The R/W signal indicates the direction of the data transfer. The DS signal is the timing reference
for all data transfers and typically has a duty cycle of 50%. A read cycle is indicated by asserting R/
W High with a falling edge on DS. A write cycle is indicated by asserting R/W Low with a rising
edge on DS.
Both cycles require the CS signal to be Low and the Address pins to be actively driven by the
microprocessor. Note that CS and DS can be connected together in Motorola mode. In a write cycle
the data bus is driven by the microprocessor. In a read cycle the bus is driven by the LXT386.
Intel Interface
The Intel interface is selected by asserting the MOT/INTL pin High. The LXT386 supports non-
multiplexed interfaces with separate address and data pins when MUX is asserted Low, and
multiplexed interfaces when MUX is asserted High. The address is latched in on the falling edge of
ALE. In non-multiplexed mode, ALE should be pulled High. R/W is used as the RD signal and DS
is used as the WR signal. A read cycle is indicated to the LXT386 when the processor asserts RD
Low while the WR signal is held High. A write operation is indicated to the LXT386 by asserting
WR Low while the RD signal is held High. Both cycles require the CS signal to be Low.
Motorola Interface
Datasheet