DJLXT386LE.B2 S E001 Intel, DJLXT386LE.B2 S E001 Datasheet - Page 26

• Manufacturer Part Number: DJLXT386LE.B2 S E001
• Manufacturer: Intel

Specifications of DJLXT386LE.B2 S E001

• Lead Free Status / RoHS Status: Not Compliant

LXT386 — QUAD T1/E1/J1 Transceiver
3.2.2
3.2.2.1
3.2.2.2
3.2.3
26
Alarm Indication Signal (AIS) Detection
The AIS detection is performed by the receiver independent of any loopback mode. This feature is
available in host mode only. Because there is no clock in data recovery mode, AIS detection will
not work in that mode. AIS requires MCLK to have clock applied, since this function depends on
the clock to count the number of ones in an interval.
E1 Mode
One detection mode suitable for both ETSI and ITU is available when the
cleared to zero. If the LACS register bit is set to one, see errata 10.3 to implement this:
ETSI ETS300233 and G.775 detection
The AIS condition is declared when the received data stream contains less than 3 zeros within a
period of 512 bits.
The AIS condition is cleared when 3 or more zeros within 512 bits are detected.
T1 Mode
ANSI T1.231 detection is employed.
The AIS condition is declared when less than 9 zeros are detected in any string of 8192 bits. This
corresponds to a 99.9% ones density over a period of 5.3ms.
The AIS condition is cleared when the received signal contains 9 or more zeros in any string of
8192 bits.
In unipolar I/O mode with HDB3/B8ZS decoding, the LXT386 reports bipolar violations on
RNEG/BPV for one RCLK period for every HDB3/B8ZS code violation that is not part of the zero
code substitution rules. In AMI mode, all bipolar violations (two consecutive pulses with the same
polarity) are reported at the BPV output.
In Service Code Violation Monitoring
LACS
register bits are
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