DJLXT386LE.B2 S E001 Intel, DJLXT386LE.B2 S E001 Datasheet - Page 25

• Manufacturer Part Number: DJLXT386LE.B2 S E001
• Manufacturer: Intel

Specifications of DJLXT386LE.B2 S E001

• Lead Free Status / RoHS Status: Not Compliant

3.2.1
3.2.1.1
3.2.1.2
3.2.1.3
Datasheet
Loss of Signal Detector
The loss of signal detector in the LXT386 uses a dedicated analog and digital loss of signal
detection circuit. It is independent of its internal data slicer comparators and complies to the latest
ITU G.775 and ANSI T1.231 recommendations. Under software control, the detector can be
configured to comply to the ETSI ETS 300 233 specification (
the LXT386 supports LOS per G.775 for E1 and ANSI T1.231 for T1 operation.
The receiver monitor loads a digital counter at the RCLK frequency. The counter is incremented
each time a zero is received, and reset to zero each time a one (mark) is received. Depending on the
operation mode, a certain number of consecutive zeros sets the LOS signal. The recovered clock is
replaced by MCLK at the RCLK output with a minimum amount of phase errors. MCLK is
required for receive operation. When the LOS condition is cleared, the LOS flag is reset and
another transition replaces MCLK with the recovered clock at RCLK. RPOS/RNEG will reflect the
data content at the receiver input during the entire LOS detection period for that channel.
E1 Mode
In G.775 mode a loss of signal is detected if the signal is below 200mV (typical) for 32 consecutive
pulse intervals. When the received signal reaches 12.5% ones density (4 marks in a sliding 32-bit
period) with no more than 15 consecutive zeros and the signal level exceeds 250mV (typical), the
LOS flag is reset and another transition replaces MCLK with the recovered clock at RCLK.
In ETSI 300 233 mode, a loss of signal is detected if the signal is below 200mV for 2048
consecutive intervals (1 ms). The LOS condition is cleared and the output pin returns to Low when
the incoming signal has transitions when the signal level is equal or greater than 250mV for more
than 32 consecutive pulse intervals. This mode is activated by setting the LACS register bit to one.
If it is necessary to use AIS with LOS, see errata 10.3 for a way to implement this.
T1 Mode
The T1.231 LOS detection criteria is employed. LOS is detected if the signal is below 200mV for
175 contiguous pulse positions. The LOS condition is terminated upon detecting an average pulse
density of 12.5% over a period of 175 contiguous pulse positions starting with the receipt of a
pulse. The incoming signal is considered to have transitions when the signal level is equal or
greater than 250mV.
Data Recovery Mode
In data recovery mode the LOS digital timing is derived from a internal self timed circuit. RPOS/
RNEG stay active during loss of signal. The analog LOS detector complies with ITU-G.775
recommendation. The LXT386 monitors the incoming signal amplitude. Any signal below 200mV
for more than 30μs (typical) will assert the corresponding LOS pin. The LOS condition is cleared
when the signal amplitude rises above 250mV. The LXT386 requires more than 10 and less than
255 bit periods to declare a LOS condition in accordance to ITU G.775.
QUAD T1/E1/J1 Transceiver — LXT386
LACS
Register). In hardware mode,
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