DJLXT386LE.B2 S E001 Intel, DJLXT386LE.B2 S E001 Datasheet - Page 69

• Manufacturer Part Number: DJLXT386LE.B2 S E001
• Manufacturer: Intel

Specifications of DJLXT386LE.B2 S E001

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
Address setup time to latch
Valid address latch pulse width
Latch active to active write setup time
Chip select setup time to active write
Chip select hold time from inactive write
Address hold time from inactive ALE
Data valid to write active setup time
Data hold time to active write
Address setup time to WR inactive
Address hold time from WR inactive
AD7-AD0
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
2. C
3. These times don’t apply for Reset Register 0Ah, since RDY line goes low once during the cycle. Please refer to Reset
Operation and Host Mode sections for more information.
Figure 22. Multiplexed Intel Read Timing
Table 47. Intel Mode Write Timing Characteristics (Sheet 1 of 2)
L
RDY
= 100pF on D0-D7, all other outputs are loaded with 50pF.
ALE
INT
CS
RD
Tristate
Parameter
tSALR
2
tVL
ADDRESS
tDRDY
tHALR
tSLR
tSCSR
tPRD
Thcsw
Tscsw
Thalw
Tsalw
Thdw
Thaw
Tsdw
Tsaw
Sym
Tslw
Tvl
Min
10
30
10
40
30
0
0
5
2
6
tVRDY
tVRD
Typ
–
–
–
–
–
–
–
–
–
QUAD T1/E1/J1 Transceiver — LXT386
1
DATA OUT
Max
–
–
–
–
–
–
–
–
–
tHSCR
tDRDY
tZRD
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tINT
Test Conditions
Tristate
tRDYZ
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