DJLXT386LE.B2 S E001 Intel, DJLXT386LE.B2 S E001 Datasheet - Page 65

• Manufacturer Part Number: DJLXT386LE.B2 S E001
• Manufacturer: Intel

Specifications of DJLXT386LE.B2 S E001

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
3 dB bandwidth
Input voltage range
Output voltage range
Master clock frequency
Master clock tolerance
Master clock duty cycle
Output pulse width
Transmit clock frequency
Transmit clock tolerance
Transmit clock burst rate
Transmit clock duty cycle
E1 TPOS/TNEG pulse width (RZ mode)
TPOS/TNEG to TCLK setup time
TCLK to TPOS/TNEG hold time
Delay time OE Low to driver High Z
Delay time TCLK Low to driver High Z
Table 42. Analog Test Port Characteristics
Table 43. Transmit Timing Characteristics
Figure 18. Transmit Clock Timing Diagram
Parameter
Parameter
TNEG
TPOS
TCLK
E1
T1
E1
T1
E1
T1
At13db
At2ov
At1iv
Sym
Tmpwe1
MCLK
MCLK
Tclke1
Tclkt1
Tclkb
Sym
Toez
Tclkt
Tsut
Tdc
Tht
Ttz
Tw
Tw
–
–
Min
0
0
-
-100
Min
219
291
236
-50
40
10
20
20
50
–
–
-
-
-
-
tSUT
Typ
5
2.048
1.544
2.048
1.544
-
-
Typ
244
324
60
–
–
–
–
–
–
-
-
-
QUAD T1/E1/J1 Transceiver — LXT386
Max
VCC
VCC
Max
100
269
356
+50
252
60
20
90
75
-
–
–
1
-
-
-
-
tHT
MHz
Unit
Unit
MHz
MHz
ppm
MHz
MHz
ppm
MHz
ns
ns
ns
ns
ns
μs
μs
V
V
%
%
Gapped transmit clock
NRZ mode
RZ mode (TCLK = H for
>16 clock cycles)
Test Condition
Test Condition
65