DJLXT386LE.B2 S E001 Intel, DJLXT386LE.B2 S E001 Datasheet - Page 34

• Manufacturer Part Number: DJLXT386LE.B2 S E001
• Manufacturer: Intel

Specifications of DJLXT386LE.B2 S E001

• Lead Free Status / RoHS Status: Not Compliant

LXT386 — QUAD T1/E1/J1 Transceiver
3.7
3.7.1
3.7.2
34
Figure 9. Analog Loopback
Figure 10. Digital Loopback
Loopbacks
The LXT386 offers three loopback modes for diagnostic purposes. In hardware mode, the loopback
mode is selected with the LOOPn pins. In software mode, the ALOOP, DLOOP and RLOOP
registers are employed.
When selected, the transmitter outputs (TTIP & TRING) are connected internally to the receiver
inputs (RTIP & RRING) as shown in
RNEG pins for the corresponding transceiver. Note that signals on the RTIP & RRING pins are
ignored during analog loopback.
Digital Loopback
The digital loopback function is available in software and hardware mode. When selected, the
transmit clock and data inputs (TCLK, TPOS & TNEG) are looped back and output on the RCLK,
RPOS & RNEG pins
the TTIP & TRING pins. Note that signals on the RTIP & RRING pins are ignored during digital
loopback.
Analog Loopback
RNEG
TNEG
RPOS
RNEG
TPOS
TNEG
RPOS
RCLK
TPOS
TCLK
RCLK
TCLK
* If Enabled
* If Enabled
(Figure
JA*
JA*
JA*
JA*
10). The data presented on TCLK, TPOS & TNEG is also output on
Recovery
Timing &
Control
Timing
Figure
Recovery
Timing &
Control
Timing
9. Data and clock are output at RCLK, RPOS &
TTIP
TRING
RTIP
RRING
TTIP
TRING
RTIP
RRING
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