DJLXT386LE.B2 S E001 Intel, DJLXT386LE.B2 S E001 Datasheet - Page 22

• Manufacturer Part Number: DJLXT386LE.B2 S E001
• Manufacturer: Intel

Specifications of DJLXT386LE.B2 S E001

• Lead Free Status / RoHS Status: Not Compliant

LXT386 — QUAD T1/E1/J1 Transceiver
3.0
3.1
22
Functional Description
Figure 1 is a simplified block diagram of the LXT386. The LXT386 is a fully integrated quad line
interface unit designed for T1 1.544 Mbps and E1 2.048 Mbps short haul applications.
Each transceiver front end interfaces with four lines, one pair for transmit, one pair for receive.
These two lines comprise a digital data loop for full duplex transmission.
The LXT386 can be controlled through hard-wired pins or by a microprocessor through a serial or
parallel interface (Host mode).
The transmitter timing reference is TCLK, and the receiver reference clock is MCLK. The LXT386
is designed to operate without any reference clock when used as an analog front-end (line driver
and data recovery). MCLK is mandatory if the on chip clock recovery capability is used. All four
clock recovery circuits share the same reference clock defined by the MCLK input signal.
Initialization
During power up, the transceiver remains static until the power supply reaches approximately 60%
of VCC. During power-up, an internal reset sets all registers to their default values and resets the
status and state machines for the LOS.
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