AM79C976KI AMD (ADVANCED MICRO DEVICES), AM79C976KI Datasheet - Page 114

• Manufacturer Part Number: AM79C976KI
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C976KI

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Not Compliant

The PCI Command register is read and written by the
host.
Bit
15-10
9
8
7
6
114
Name
RES
FBTBEN
SERREN
RES
PERREN
ros; write operations have no ef-
fect.
this bit is set to 1, the Am79C976
controller
Back-to-Back cycles. When this
bit is cleared to 0, the Am79C976
controller will not generate Fast
Back-to-Back cycles.
FBTBEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
sertion of the SERR pin. SERR is
disabled
cleared. SERR will be asserted
on detection of an address parity
error and if both SERREN and
PERREN (bit 6 of this register)
are set.
H_RESET and is not effected by
S_RESET or by setting the STOP
bit.
ros; write operations have no ef-
fect.
Enables the parity error response
functions. When PERREN is 0
and the Am79C976 controller de-
tects a parity error, it only sets the
Detected Parity Error bit in the
PCI Status register. When PER-
REN is 1, the Am79C976 control-
ler
detection of a data parity error. It
also sets the DATAPERR bit (PCI
Status register, bit 8), when the
data parity error occurred during
a master cycle. PERREN also
enables reporting address parity
errors through the SERR pin and
the SERR bit in the PCI Status
register.
Description
Reserved locations. Read as ze-
Fast Back-to-Back Enable. When
SERR Enable. Controls the as-
SERREN
Reserved location. Read as ze-
Parity Error Response Enable.
asserts
when
will
is
PERR
generate
SERREN
cleared
P R E L I M I N A R Y
on
Fast
Am79C976
the
by
is
5
4
3
2
1
VGASNOOP
MWIEN
SCYCEN
BMEN
MEMEN
MWIEN is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
For accesses to the Expansion
ROM, the host must program the
PCI Expansion ROM Base Ad-
dress register at offset 30h with a
valid memory address before set-
PERREN
H_RESET and is not affected by
S_RESET or by setting the STOP
bit.
VGA Palette Snoop. Read as ze-
ro; write operations have no ef-
fect.
Memory Write and Invalidate Cy-
cle Enable. When this bit is set to
1, the Am79C976 controller will
generate Memory Write and In-
validate (MWI) cycles when ap-
propriate. When the bit is cleared
to 0, the device will generate
Memory Write cycles instead of
MWI cycles.
Special Cycle Enable. Read as
zero; write operations have no ef-
fect. The Am79C976 controller
ignores all Special Cycle opera-
tions.
Bus
BMEN enables the Am79C976
controller to become a bus mas-
ter on the PCI bus. The host must
set BMEN before setting the INIT
or STRT bit in CSR0 of the
Am79C976 controller.
BMEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
The Am79C976 controller will ig-
nore all memory accesses when
MEMEN is cleared. The host
must set MEMEN before the first
memory access to the device.
For memory mapped I/O, the
host must program the PCI Mem-
ory Mapped I/O Base Address
register with a valid memory ad-
dress before setting MEMEN.
Memory Space Access Enable.
Master
is
Enable.
cleared
9/14/00
Setting
by