AM79C976KI AMD (ADVANCED MICRO DEVICES), AM79C976KI Datasheet - Page 241

• Manufacturer Part Number: AM79C976KI
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C976KI

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Not Compliant

The following tables describe the transmit descriptor
bits in more detail.
9/14/00
Offset
Offset
0
2
2
2
2
2
2
2
0Ch
1Ch
00h
04h
08h
10h
14h
18h
11-10
15-0
Bit
15
14
13
12
9
8
OWN
31
30
TBADR[15:0]
ADD_FCS
Name
LTINT
OWN
ENP
STP
ADD_
FCS
29
Table 114.
Table 115.
LTINT
28
Transmit Buffer Address. This field contains the high order bits of the address of the
Transmit buffer that is associated with this descriptor.
This bit indicates whether the descriptor entry is owned by the host (OWN = 0) or by
the Am79C976 controller (OWN = 1). The host sets the OWN bit after filling the buffer
pointed to by the descriptor entry. The Am79C976 controller clears the OWN bit after
transmitting the contents of the buffer. Both the Am79C976 controller and the host
must not alter a descriptor entry after it has relinquished ownership.
Reserved location
ADD_FCS dynamically controls the generation of FCS on a frame by frame basis.
This bit should be set with the ENP bit. However, for backward compatibility, it is
recommended that this bit be set for every descriptor of the intended frame. When
ADD_FCS is set, the state of DXMTFCS is ignored and transmitter FCS generation is
activated. When ADD_FCS is cleared to 0, FCS generation is controlled by
DXMTFCS. When APAD_XMT (CSR4, bit 11) is set to 1, the setting of ADD_FCS has
no effect. ADD_FCS is set by the host, and is not changed by the Am79C976
controller. This is a reserved bit in the C-LANCE (Am79C90) controller.
Last Transmit Interrupt. When enabled by the LTINTEN bit (CSR5, bit 14), LTINT is
used to suppress interrupts after selected frames have been copied to the transmit
FIFO. When LTINT is cleared to 0 and ENP is set to 1, the Am79C976 controller will
not set TINT (CSR0, bit 9) after the corresponding frame has been copied to the
transmit FIFO. TINT will only be set when the last descriptor of a frame has both
LTINT and ENP set to 1. When LTINTEN is cleared to 0, the LTINT bit is ignored.
Reserved.
Start of Packet indicates that this is the first buffer to be used by the Am79C976
controller for this frame. It is used for data chaining buffers. The STP bit must be set
in the first buffer of the frame, or the Am79C976 controller will skip over the descriptor
and poll the next descriptor(s) until the OWN and STP bits are set. STP is set by the
host and is not changed by the Am79C976 controller.
End of Packet indicates that this is the last buffer to be used by the Am79C976
controller for this frame. It is used for data chaining buffers. If both STP and ENP are
set, the frame fits into one buffer and there is no data chaining. ENP is set by the host
and is not changed by the Am79C976 controller.
P R E L I M I N A R Y
27-26
Transmit Descriptor (SWSTYLE = 5)
Transmit Descriptor, SWSTYLE = 0
Am79C976
STP
25
.
TBADR[63:32]
USER SPACE
USER SPACE
USER SPACE
TBADR[31:0]
Reserved
ENP
24
23
Description
KILL
22
21-18
TCC[1:0]
17-16
TCI[15:0]
BCNT
15-0
241