AM79C976KI AMD (ADVANCED MICRO DEVICES), AM79C976KI Datasheet - Page 91

• Manufacturer Part Number: AM79C976KI
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C976KI

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Not Compliant

The effects of the FCCMD bit are summarized in
Table 14.
Programming the Pause Length Register
When the host CPU changes the contents of the Pause
Length Register, it must make sure that no Pause
frame is transmitted while the register is being updated.
If the host CPU can not control the state of the FC pin,
it can clear the FCPEN pin so that the FC pin will be ig-
nored. It can then poll the PAUSE_PENDING bit in the
Status0 Register until that bit is 0. When FCPEN and
PAUSE_PENDING are both 0, it is safe to write to the
Pause Length Register.
PAUSE Frame Reception
The ability to respond to received pause frames, or
pause ability, is controlled independently from the
transmission of pause frames. When pause ability is
enabled, the receipt of a pause frame causes the de-
vice to stop transmitting for a time period that is deter-
mined by the contents of the pause frame.
Pause ability is enabled by Negotiate Pause Ability
(NPA, FLOW_CONTROL, bit 19) and Force Pause
Ability (FPA, FLOW_CONTROL, bit 20). If the FPA bit
is set, pause ability is enabled regardless of the Pause
Ability state of the link partner. If the NPA bit is set and
the FPA bit is not set, pause ability is enabled only if the
auto-negotiation process determines that the link part-
ner also supports 802.3x flow control.
9/14/00
Transition
FCCMD
0 to 1
1 to 0
0 to 1
1 to 0
0 to 1
1 to 0
Table 14. FCCMD Bit Functions
FIXP
X
X
1
1
0
0
Duplex
Mode
Half
Half
Full
Full
Full
Full
Enable back pressure
Disable back pressure
Send pause frame with
request operand equal to
the contents of the Pause
Length register.
Automatically clear
FCCMD to 0.
No action. (FCCMD is
cleared automatically
when FIXP = 1.)
Send pause frame with
request operand equal to
0FFFFh.
Send pause frame with
request operand equal to
0000h.
Action
P R E L I M I N A R Y
Am79C976
The auto-polling state machine is extended to read the
external PHY Status registers at register locations 1, 4,
and 5. (The contents of these registers are defined in
the IEEE P802.3u specification.) From Register 1 the
state machine obtains the link status and auto-negotia-
tion status as well as Jabber and Remote Fault indica-
tions. If auto negotiation is complete, the logic uses the
Technology Ability fields of the Auto-Negotiation Adver-
tisement register (Register 4) and the Auto-Negotiation
Link Partner Ability register (Register 5) to determine
the network speed and duplex mode and the flow con-
trol status. The MAC device will be put into the speed
and duplex mode for the highest common ability that
the PHY and its link partner share. If full-duplex mode
is selected and the PAUSE bits are set in both Register
4 and Register 5, pause ability will be enabled so that
the MAC will be able to respond to MAC Control
PAUSE frames as described in the IEEE P802.3x
specification.
A MAC Control PAUSE frame is any valid frame with
the following:
I A destination address field value equal to the MAC’s
I A Length/Type field value equal to 88-08, and
I A MAC Control Opcode field value equal to 0001.
If such a frame is received while pause ability is en-
abled, the MAC device will wait until the end of the
frame currently being transmitted (if any) and then stop
transmitting for a time equal to the value of the
request_operand field (octets 17 and 18) multiplied by
512-bit times.
If another MAC Control PAUSE frame is received
before the Pause timer has timed out, the Pause timer
will be reloaded from the request_operand field of the
new frame so that the new frame overrides the earlier
one.
Received MAC Control PAUSE frames are handled
completely by the Am79C976 hardware. They are not
passed on to the host computer. However, MAC Con-
trol frames with opcodes not equal to 0001h are treated
as normal frames, except that their reception causes
the Unsupported Opcodes counter to be incremented.
Since the host computer does not receive MAC Control
PAUSE frames, 32-bit MIB counters have been added
to record the following:
I MAC Control Frames received
I Unsupported Opcodes received
I PAUSE frames received
physical address or equal to the reserved multicast
address 01-80-C2-00-00-01,
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