AM79C976KI AMD (ADVANCED MICRO DEVICES), AM79C976KI Datasheet - Page 93

• Manufacturer Part Number: AM79C976KI
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C976KI

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Not Compliant

If SWSTYLE = 2 or 3, tag bits are shifted in the order
B14, B13, ... , B0.
Because of the order in which frame tag bits are shifted
in, if the tag is shorter than 15 bits, the tag data will be
placed in the least significant portion of the Receive
Frame Tag field of the RX descriptor, and the most sig-
nificant bits of the field will be cleared to zeros.
RXFRTGE need not be a continuous signal. It can tog-
gle on and off so that the tag data can be shifted in at a
slower rate than the frequency of RX_CLK. The length
of the frame tag is determined by the number of
External Memory Interface
The Am79C976 controller contains an External Mem-
ory Interface that supports Flash (or EPROM) devices
as boot devices, as well as SSRAM for frame data stor-
age. The controller provides read and write access to
Flash or EPROM. No glue logic is required for the
memory interface.
The Am79C976 device contains a built-in self test sys-
tem (MBIST) that can be programmed to run a diag-
nostics test on the external SSRAM.
The external SSRAM is organized around a 32-bit data
bus. The memory can be as large as 1M X 32 bits. The
memory devices can be either JEDEC standard Pipe-
line Burst Synchronous Static RAM devices (PB-SS-
RAM) or ZBT™ Synchronous Static RAM (ZBT-
SSRAM) with pipelined outputs. The SRAM_TYPE
field of the CTRL0 Register must be initialized to
dicate which type of SSRAM is actually used.
9/14/00
MIIRXFRTGD
MIIRXFRTGE
RX_CLK
RX_DV
SF/BD
Figure 35. MII Receive Frame Tagging
P R E L I M I N A R Y
Am79C976
in-
RX_CLK cycles during which RXFRTGE is asserted
before the end of the frame arrives (with a maximum of
15 bits for SWSTYLE 2 or 3 or a maximum of 32 bits for
SWSTYLE 5). The last bit of the Receive Frame Tag
must be shifted into the RXFRTGD input at least one
RX_CLK cycle before RX_DV is de-asserted.
The Receive Frame Tagging feature is enabled by the
RXFRTGEN bit in CMD3 Register. When this bit is
cleared to 0, the Receive Frame Tag field of the RX de-
scriptor will be filled with zeros.
The contents of the SRAM_TYPE field are defined in
Table 15.
The width of the Flash memory (or EPROM) is 8 bits.
The memory can be as large as 16M X 8 bits.
The external memory bus uses the same address,
data, and control pins to access both Flash and
SSRAM memory, but it has separate chip select (or
chip enable) pins so that only one device can be se-
lected at a time. FLCS selects the Flash memory, while
ERCE selects the SSRAM. The Flash memory must
not be accessed when the Am79C976 controller is run-
ning (when the RUN bit in CMD0 is set to 1). Any ac-
cess to the Flash memory clears the RUN bit and
thereby abruptly stops all network and DMA opera-
tions.
ERA[19:0] provides 20 bits of address for the SSRAM
and the lower 20 bits of address for the Flash memory.
SRAM_TYPE[1:0]
Table 15. SRAM_TYPE Field Encoding
00
01
10
11
External Memory Type
Pipelined Burst
Reserved
Reserved
ZBT
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