AM79C976KI AMD (ADVANCED MICRO DEVICES), AM79C976KI Datasheet - Page 124

• Manufacturer Part Number: AM79C976KI
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C976KI

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Not Compliant

Memory-Mapped Registers
The Memory-Mapped Registers give the host CPU ac-
cess to all programmable features of the Am79C976
device. These registers are mapped directly into PCI
memory space so that any programmable feature can
be accessed with a single PCI memory read or write
transaction. Data in these registers can be accessed
as a single byte, a 16-bit word, or a 32-bit double word.
In addition, the Am79C976 controller’s memory is
prefetchable, which allows burst read and write opera-
tions. Accesses to consecutive registers or to registers
logically wider than double word (BADX, BADR, PADR,
etc.) may be treated as a single block move to take ad-
vantage of the PCI burst.
Registers that are logically wider than a double word
are shown in the register descriptions as a single reg-
ister. These may be accessed using multiple smaller
accesses or with a single burst access.
Some registers that are smaller than a double word in
width (STVAL, PADR[47:32], XMT_RING_LEN,
RCV_RING_LEN) are placed in the memory map in the
lower half of a double word. The upper half ignores
writes and reads back zeros (STVAL, PADR[47:32]) or
ones (XMT_RING_LEN, RCV_RING_LEN) as appro-
priate for sign extension. This allows these registers to
be accessed with double word reads and writes.
Memory-mapped registers can be initialized with data
loaded from the serial EEPROM.
The command and interrupt enable registers (CMD0,
CMD2, CMD3, CMD7, and INTEN0) use a write access
technique that in this document is called command
style access. Command style access allows the host
CPU to write to selected bits of a register without alter-
ing bits that are not selected. Command style registers
are divided into 4 bytes that can be written indepen-
dently. The high order bit of each byte is the ’value’ bit
that specifies the value that will be written to selected
bits of the register. The 7 low order bits of each byte
make up a bit map that selects which register bits will
be altered. If a bit in the bit map is set to 1, the corre-
sponding bit in the register will be loaded with the con-
tents of the value bit. If a bit in the bit map is cleared to
0, the corresponding bit in the register will not be al-
tered.
For example, if the value 10011010b is written to the
least significant byte of a command style register, bits
1, 3, and 4 of the register will be set to 1, and the other
bits will not be altered. If the value 00011010b is written
to the same byte, bits 1, 3, and 4 will be cleared to 0,
and the other bits will not be altered.
124
P R E L I M I N A R Y
Am79C976
In the worst case it takes two write accesses to write to
all of the bits in a command style register. One access
writes to all bits that should be set to 1, and the other
access writes to all bits that should be cleared to 0.
The EEPROM loading logic bypasses the command
style access logic and treats command style registers
just like the other writable memory-mapped registers.
The value bits are ignored and the contents of the bit
map fields are written directly into the corresponding
registers. For example, if the EEPROM logic loads the
value 00011010b into the least significant byte of a com-
mand style register, bits 1, 3, and 4 of the register will be
set to 1, and bits 0, 2, 5, and 6 will be cleared to 0.
In the following register descriptions, the offset listed
for each register is the offset relative to the contents of
the PCI Memory-Mapped I/O Base Address Register.
MIB Offset
Offset 28h
This read-only register contains the offset of the block
of statistics counters. For the Am79C976 device the
content of this register is fixed at 200h. The contents of
the MIB Offset Registers and therefore the locations of
statistics counter blocks in other PCnet family devices
may be different. Therefore, software should calculate
the address of a particular MIB counter by adding the
contents of the Memory-Mapped I/O Base Address
Register plus the contents of this register plus the offset
shown in Table 7 on page 76 or Table 8 on page 78.
AP_VALUE0: Auto-Poll Value0 Register
Offset 0A8h
The contents of this register are cleared to 0 when the
RST pin is asserted. The register is not cleared at the
start of a serial EEPROM read operation or after a se-
rial EEPROM read error.
AP_VALUE1: Auto-Poll Value1 Register
Offset 0AAh
The contents of this register are cleared to 0 when the
RST pin is asserted. The register is not cleared at the
start of a serial EEPROM read operation or after a se-
rial EEPROM read error.
Table 26. AP_VALUE0: Auto-Poll Value0 Register
15-0 AP_VALUE0
Bit
Name
This register contains the results of
the automatic polling of the user-
selectable external PHY register,
AP_REG0.
Description
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