AM79C976KI AMD (ADVANCED MICRO DEVICES), AM79C976KI Datasheet - Page 29

• Manufacturer Part Number: AM79C976KI
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C976KI

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Not Compliant

If the CLKSEL0 and CLKSEL1 pins are not both held
low, a 20-, 25-, or
nected to the XCLK pin, and the XTAL1 and XTAL2
pins should be connected to VSS.
XTAL1 and XTAL2 are not 5-volt tolerant pins.
XTAL2
Crystal
If the CLKSEL0 and CLKSEL1 pins are both held low,
a 25 MHz crystal should be connected between the
XTAL1 pin and the XTAL2 pin. This crystal controls the
frequency of the internal clock generator circuit.
If either the CLKSEL0 or the CLKSEL1 pin or both are
held high, a 20-, 25-, or
connected to the XCLK pin, and the XTAL1 and XTAL2
pins should be connected to VSS.
XTAL1 and XTAL2 are not 5-volt tolerant pins.
PHY_RST
PHY Reset
PHY_RST is an output pin that is used to reset the ex-
ternal PHY. This output eliminates the need for a
fan-out buffer for the PCI RST signal, provides polarity
for the specific PHY used, and prevents the resetting of
the PHY when the PG input is LOW. The output polarity
is determined by the RST_POL bit (CMD3, bit0), which
can be loaded from the EEPROM.
The length of time for which the PHY_RST pin is as-
serted depends on the number of registers that are
loaded from the EEPROM and the order in which the
registers are loaded. Immediately after the RST_POL
bit is loaded from the EEPROM, the PHY_RST pin is
asserted. When the last register has been loaded from
the EEPROM, the PHY_RST pin is deasserted. Each
register loaded after the RST_POL bit is loaded adds
about 240 µs to the time that PHY_RST is asserted. If
the PHY_RST pin is used to reset an external PHY, the
user should program the EEPROM to make sure that
PHY_RST is asserted long enough to meet the require-
ments of the PHY. The user can insert dummy writes to
offset 28h to extend the reset period.
FC
Flow Control
The Flow Control input signal controls when MAC Con-
trol Pause Frames are sent or when half-duplex back
pressure is asserted.
EEPROM Interface
EECS
EEPROM Chip Select
This pin is designed to directly interface to a serial EE-
PROM that uses the 93Cxx EEPROM interface proto-
9/14/00
33
1
/
3
-MHz
33
1
/
3
-MHz
clock source must be con-
clock source must be
P R E L I M I N A R Y
Output
Output
Output
Input
Am79C976
col. EECS is connected to the EEPROM’s chip select
pin. It is controlled by either the Am79C976 controller
during command portions of a read of the entire EE-
PROM, or indirectly by the host system by writing to
BCR19, bit 2.
EEDI
EEPROM Data In
This pin is designed to directly interface to a serial EE-
PROM that uses the 93Cxx EEPROM interface proto-
col. EEDI is connected to the EEPROM’s data input
pin. It is controlled by either the Am79C976 controller
during command portions of a read of the entire EE-
PROM, or indirectly by the host system by writing to
BCR19, bit 0.
Note: The EEDI pin is multiplexed with the LED0 pin.
EEDO
EEPROM Data Out
This pin is designed to directly interface to a serial EE-
PROM that uses the 93Cxx EEPROM interface proto-
col. EEDO is connected to the EEPROM’s data output
pin. It is controlled by either the Am79C976 controller
during command portions of a read of the entire EE-
PROM, or indirectly by the host system by reading from
BCR19, bit 0.
Note: The EEDO pin is multiplexed with the LED3 and
RXFRTGD pins.
EESK
EEPROM Serial Clock
This pin is designed to directly interface to a serial EE-
PROM that uses the 93Cxx EEPROM interface proto-
col. EESK is connected to the EEPROM’s clock pin. It
is controlled by either the Am79C976 controller directly
during a read of the entire EEPROM, or indirectly by
the host system by writing to BCR19, bit 1.
Note: The EESK pin is multiplexed with the LED1 pin.
External Memory Interface
ERA[19:0]/FLA[19:0]
External Memory Address [19:0]
The ERA[19:0] pins provide addresses for both the ex-
ternal SSRAM and the external boot ROM device.
All ERA[19:0] pin outputs are forced to a constant level
to conserve power while no access on the External
Memory Bus is being performed.
FLA[23:20]
Boot ROM (Flash) Address [23:20]
The FLA[23:20] pins provide the 4 most significant bits
of the address for the external boot ROM device.
Output
Output
Output
Output
Input
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