ADM7001XACT1XP Lantiq, ADM7001XACT1XP Datasheet
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ADM7001XACT1XP
Specifications of ADM7001XACT1XP
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ADM7001XACT1XP Summary of contents
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Edition 2005-09-12 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2005. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of ...
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... Single Ethernet 10/100M PHY Revision History: 2005-09-12, Rev. 1.07 Previous Version: Page/Date Subjects (major changes since last revision) 2003-03-05 Rev. 1.0: First release of ADM7001 2003-04-08 Rev. 1.01: Register Modifications and Pin updates 2003-07-24 Rev. 1.02: The following sections were updated: 1.2, 1.3, 2.1, 2.2.1, 2.2.5, 2.2.7, 2.2.8, 2.2.8, 4.1, 4.2.3-4, 4.2.11-12, 4.3.4, 4.3.9, 4.3.11, 4.3.12, & ...
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... MII/RMII/GPSI Interface, 16 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.6 Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.7 Clock Signals, 6 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.8 LED Interface, 4 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.9 Regulator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1 10/100M PHY Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.1 100Base-X Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.2 100Base-TX Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.3 100Base-TX Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.1.4 100Base-FX Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.1.5 100Base-FX Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1.6 10Base-T Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3 ...
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Receive Path for MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 ADM7001 Block Diagram 10 Figure 2 Pin Diagram 11 Figure 3 100Base-X Block Diagram and Data Path 26 Figure 4 10Base-T Block Diagram and Data Path 31 Figure 5 RMII Signal Diagram 34 Figure 6 ...
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List of Tables Table 1 Abbreviations for Pin Type 12 Table 2 Abbreviations for Buffer Type 12 Table 3 Twisted Pair Interface, 5 Pins 13 Table 4 Digital Ground/Power, 7 Pins 14 Table 5 Ground and Power, 5 Pins 15 ...
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... Features and Block Diagram. 1.1 Overview The ADM7001 is a single chip one port 10/100M PHY, which is designed for today’s low cost and low power dual speed application. It supports auto sensing 10/100 Mbps ports with on-chip clock recovery and base line wander correction including integrated MLT-3 functionality for 100 Mbps operation, and also supports Manchester Code Converter with on chip clock recovery circuitry for 10 Mbps functionality ...
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Built-in Clock Generator and Power On Reset Signal to save system cost. • 48 LQFP without regulator. • Supports Power saving function. • Supports Parallel LED output. Data Sheet 9 ADM7001 Data sheet Product Overview Rev. 1.07, 2005-09-12 ...
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Block Diagram Figure 1 ADM7001 Block Diagram Data Sheet 10 ADM7001 Data sheet Product Overview Rev. 1.07, 2005-09-12 ...
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Interface Description 2.1 Pin Diagram VCCO_25 GNDIK GNDO VCCIK_25 Figure 2 Pin Diagram 2.2 Pin Description Note: For those pins, which have multiple functions, pin name is separated by slash ("/"). If not specified, all signals are default to ...
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Table 1 Abbreviations for Pin Type Abbreviations Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I bidirectional input/output signal. AI Input. Analog levels. AO Output. Analog levels. AI/O Input or Output. Analog levels. PWR ...
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Twisted Pair Interface, 5 Pins Table 3 Twisted Pair Interface, 5 Pins Pin or Ball Name No. 35 TXP 34 TXN 27 RXP 26 RXN 28 Power On Setting FXEN Fiber Mode SDP Data Sheet Pin Buffer Function Type ...
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Digital Ground/Power, 7 Pins Table 4 Digital Ground/Power, 7 Pins Pin or Ball Name No GNDO 2, 37 GNDIK 1, 18 VCCO_25 7 VCCIK_25 Data Sheet Pin Buffer Function Type Type D,GND Ground used by 3.3 V ...
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Ground and Power, 5 Pins Table 5 Ground and Power, 5 Pins Pin or Ball Name No. 41 VCC3IN 36 VCC25OUT 29 GNDTR 25 VCCA_25 32 VCCPLL_25 Data Sheet Pin Buffer Function Type Type A,PWR 3.3V Power input to ...
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Clock Input, 2 Pins Table 6 Clock Input, 2 Pins Pin or Ball Name No. 40 XI/OSCI 39 XO 2.2.5 MII/RMII/GPSI Interface, 16 pins Table 7 MII/RMII/GPSI Interface, 16 pins Pin or Ball Name No. 9 MII Mode TXCLK ...
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Table 7 MII/RMII/GPSI Interface, 16 pins (cont’d) Pin or Ball Name No. 14, 13, 12, MII Mode 11 TXD[3:0] RMII Mode TXD[3:0] GPSI Mode TXD[3:0] 10 MII Mode TXEN RMII Mode TXEN GPSI Mode TXEN 8 MII Mode TXER RMII ...
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Table 7 MII/RMII/GPSI Interface, 16 pins (cont’d) Pin or Ball Name No. 4 Power On Setting RMII_EN MII Mode RX_CLK RMII Mode CLKO50 GPSI Mode RX_CLK Data Sheet Pin Buffer Function Type Type I LVTTL RMII Enable. PD Used to ...
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... Keep Low in GPSI Mode. I TTL PHY Address Select PD Value on these 4 pins combined with PHYAD0 will be stored into ADM7001 as PHY physical address during power on reset. After power on reset, these 4 pins are output. O 8mA MII Receive Data. ...
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Table 7 MII/RMII/GPSI Interface, 16 pins (cont’d) Pin or Ball Name No. 5 Power On Setting ISOLATE MII Mode RXER RMII Mode RXER GPSI Mode N/A 15 Power On Setting GPSI GPSI/MII Mode COL RMII Mode N/A Data Sheet Pin ...
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Table 7 MII/RMII/GPSI Interface, 16 pins (cont’d) Pin or Ball Name No. 16 Power On Setting REPEATER MII Mode CRS RMII Mode N/A GPSI Mode CRS Note: LVTTL: Low Voltage TTL Level Data Sheet Pin Buffer Function Type Type I ...
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... A non-continuous clock input for management usage. ADM7001 will use this clock to sample data input on MDIO and drive data onto MDIO according to rising edge of this clock. Note: LVTTL: Low Voltage TTL Level LVTTL PHY Address bit 0. PU See RXD[3:0] description. Note: LVTTL: Low Voltage TTL Level Interrupt Default active low signal to indicate that there is interrupt event in SMI register ...
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LED Interface, 4 Pins Table 10 LED Interface, 4 Pins Pin or Ball Name No. 20 Reserved LNKACT 21 Power On Setting SPD100 Normal Mode SPDLED Data Sheet Pin Buffer Function Type Type I TTL Reserved 8mA ...
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Table 10 LED Interface, 4 Pins (cont’d) Pin or Ball Name No. 22 Power On Setting DUPFUL Normal Mode DUPLED 23 Power On Setting ANEN Normal Mode COLLED 2.2.9 Regulator Control Table 11 Regulator Control Pin or Ball Name No. ...
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... Clock synthesizer module • MII Registers • IEEE 802.3u auto negotiation The interface used for communication between PHY block and switch core is MII interface. 3.1.1 100Base-X Module ADM7001 implements 100Base-X compliant PCS and PMA, and 100Base-TX compliant TP-PMD as illustrated in Figure 3. Bypass options for each of the major functional blocks within the 100Base-X PCS provide flexibility for various applications ...
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The 100Base-X receiver consists of functional blocks required to recover and condition the 125 Mbps receive data stream. The ADM7001 implements the 100Base-X receiving state machine diagram as given in ANSI/IEEE Standard 802.3u, Clause 24. The 125 Mbps receive data ...
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Decision Feedback techniques meets the requirement of BER less than 10-12 for transmission on CAT5 twisted pair cable ranging from 0 to 140 meters. NRZI/NRZ and Serial/Parallel Decoder The recovered data is converted from NRZI to NRZ. The ...
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Table 12 Look-up Table for Translating 5B Symbols into 4B Nibbles (cont’d) PCS Code-Group[4:0] Name 11010 C 11011 D 11100 E 11101 F 11111 I 11000 J 10001 K 01101 T 0111 R 00100 H 00000 V 00001 V 00010 ...
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Should auto negotiation be disabled, the link integrity logic moves immediately to the link-up state after entering the link-ready state. Carrier Sense Carrier sense (CRS) for 100 Mbits/s operation ...
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Automatic “Signal_Detect“ Function Block When DIS_ANASDEN_N in register 18 is set to 0, ADM7001 doesn't support SDP detection in fiber mode, which is used to connect to fiber transceiver to indicate there is signal on the fiber. Instead, ADM7001 uses ...
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The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the IEEE 802.3 10Base-T standard) to determine the validity of data on the ...
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Jabber Function The jabber function monitors the ADM7001 output and disables the transmitter if it attempts to transmit a longer than legal sized packet. If TXEN is high for greater than 24ms, the 10Base-T transmitter will be disabled. Once ...
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The basic mode control register at address 0 negotiation function. When auto negotiation is disabled, the speed selection bit (bit 13) controls switching between 10 Mbps or 100 Mbps operation, while the duplex mode ...
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Figure 5 RMII Signal Diagram 3.2.2 Receive Path for 100M Figure 6 shows the relationship among REFCLK, CRSDV, RXD and RXER while receiving a valid packet. Carrier sense is detected, which causes CRSDV to assert asynchronously to REFCLK. The received ...
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Figure 7 RMII Reception with False Carrier (100M Only) A receive symbol error event is shown in packet with the exception that all di-bits are substituted with the (01) pattern. Figure 8 RMII Reception with Symbol Error 3.2.3 Receive Path ...
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Figure 10 100M RMII Transmit Diagram Data Sheet 36 ADM7001 Data sheet Function Description Rev. 1.07, 2005-09-12 ...
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Transmit Path for 10M In 10MBSE-T mode, each di-bit must be repeated 10 times by the MAC, TXEN and TXD[1:0] should be synchronous to REFCLK. When TXEN is asserted, it indicates that data on TXD[1:0] is valid for transmission. ...
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Figure 12 MII Signal Diagram 3.2.7 Receive Path for MII Figure 13 shows the relationship among RXCLK, RXDV, RXD and CRS during a reception of valid packet. Carrier sense is detected and asserted asynchronously to RXCLK by ADM7001. When ADM7001 ...
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Figure 14 MII Receive With False Carrier A receive symbol error event is shown in packet with the exception that all bits are substituted with the (0101) pattern. RXER will keep low in 10M Operation. Figure 15 MII Receive With ...
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Transmit Path for MII Figure 16 shows the relationship among TXCLK, TXEN and TXD[3:0] during a transmit event. TXEN and TXD[3:0] are synchronous to TXCLK, which is generated by MAC. TXCLK is running at 25M in 100M mode and ...
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Figure 18 GPSI Signal Diagram 3.2.10 Receive Path for GPSI Figure 19 shows the relationship among RXCLK, RXD and CRS during a receive of valid packet. Carrier sense is detected and asserted asynchronously to RXCLK by ADM7001. When ADM7001 detects ...
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Figure 20 GPSI Transmit Diagram 3.3 LED Display Register 19 is used for different mode led display. ADM7001 provides power on LED self test to minimize and ease the system test cost. All LEDs will be Off during power on ...
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... The next field signals the operation code (OP): <10> indicates read from MII management register operation, and <01> indicates write to MII management register operation. The next two fields are PHY device address and MII management register address. Both of them are 5 bits wide and the most significant bit is transferred first. ...
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... Hardware reset operation samples the pins and initializes all registers to their default values. This process includes re-evaluation of all hardware configurable registers. A software reset will reset an individual PHY and it does not latch the external pins nor reset the registers to their respective default value. ...
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Figure 23 Medium Detect Power Management Flow Chart Another way to reduce instant power is to separate the LED display period. All 4 LEDs will be divided into 4 time frame and each time frame occupies 1 us. One and ...
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Figure 24 Power and Ground Filtering Data Sheet VCCO_25 GNDIK ADM7001 GNDO VCCIK_25 QFP 48 46 Data sheet Function Description VCC25OUT(CORE) GNDPLL VCCPLL_25 GNDTR VCCA_25 Rev. 1.07, 2005-09-12 ADM7001 ...
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... Auto Negotiation Link Partner Ability ANER Auto Negotiation Expansion Register Res0 Reserved 0 GPCR Generic PHY Control/Configuration Register P10_MCR PHY 10M Module Configuration Register P100_MCR PHY 100M Module Control Register LCR LED Configuration Register IER Interrupt Enable Register PGSR PHY Generic Status Register ...
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... Symbol Description Hardware (HW) Read only ro Register is set by HW (register between input and output -> one cycle delay) Read virtual rv Physically, there is no new register, the input of the signal is connected directly to the address multiplexer. Latch high, lhsc Latch high signal at high level, clear on self clearing ...
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... RST_1, PHY Reset B Back Enable This bit controls the PHY loop back operation that isolates the network transmitter outputs (TXP and TXN) and routes the MII transmit data to the MII receive data path. This function should only be used when auto negotiation is disabled (bit12 = 0). The specific PHY (10Base-T or 100Base-X) used for this operation is determined by bits 12 and 13 ...
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... TXEN. 0 CT_0, Disable COL signal test B 1 CT_1, Enable COL signal test B Speed Selection MSB SPEED_MSB. Set to 0 all the time indicate that the PHY841F does not support 1000 Mbit/s function. Reserved Not Applicable 50 ADM7001 Data sheet Registers Description ...
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Status Register SR Status Register Data Sheet Offset ADM7001 Data sheet Registers Description Reset Value 7849 H Rev. 1.07, 2005-09-12 ...
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... FX: Set to 0 all the time to indicate that the PHY841F does not support 10M Full Duplex mode 10M Half Duplex Capable TP: Set to 1 all the time to indicate that the PHY841F does support 10M Half Duplex mode. FX: Set to 0 all the time to indicate that the PHY841F does not support ...
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... B 1 RFD_1, Remote Fault detected B Auto Negotiation Ability TP: This bit is set to 1 all the time, indicating that PHY841F is capable of auto negotiation. FX: This bit is set to 0 all the time, indicating that PHY841F is not capable of auto negotiation in Fiber Mode. 0 ANEG_0, Not capable of auto negotiation ...
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... PHY Identifier PHY_IR0 PHY Identifier Register 0 Field Bits Type PHYID 15:0 ro PHY Identifier Register 1 PHY_IR1 PHY Identifier Register 1 Field Bits Type PHYID 15:10 ro MODEL 9:4 REVID 3:0 Data Sheet Offset 02 H Description PHY-ID IEEE Address Offset 03 H Description PHY-ID 15:0 IEEE Address/Model No./Rev. No. ...
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... Data Sheet Offset 04 H Description Next Page This bit is defaults to 1, indicating that PHY841F is next page capable. Reserved Not Applicable Remote Fault This bit is written by serial management interface for the purpose of communicating the remote fault condition to the auto negotiation link partner. ...
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... TF_1, Capable of 10M Full Duplex operation B 10Base-T Half Duplex 0 TD_0, Not capable of 10M operation B 1 TD_1, Capable of 10M operation B Selector Field These 5 bits are hardwired to 00001 supports IEEE 802.3 CSMA/CD. Offset ADM7001 Data sheet Registers Description , indicating that the PHY841F B Reset Value 01E1 Rev. 1.07, 2005-09-12 H ...
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Field Bits Type NPG 15 ro ACK Res 12 LPAP 11 LPP 10 LPTA 9 TXF 8 TXD Sel 4:0 Auto Negotiation Expansion Register ANER Auto Negotiation Expansion Register Data Sheet Description ...
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Field Bits Type Res 15:5 ro PFLT 4 ro, lhsc LPNP 3 ro NXPG 2 PRCV 1 ro, lhsc LPAN 0 ro Reserved 0 Res0 Reserved 0 Field Bits Type Res 15:0 ro Table 22 Reserved Registers Register Short Name ...
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... Res7 Reserved 7 Res8 Reserved 8 Res9 Reserved 9 Res10 Reserved 10 Res11 Reserved 11 Res12 Reserved 12 Res 13 Reserved 13 Generic PHY Control/Configuration Register Note: PHY Control/Configuration Registers start from address 16 to 21. GPCR Generic PHY Control/Configuration Register Field Bits Type IFSEL 15:14 ro LBKMD 13:12 rw Res 11:10 ro FLT ...
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Field Bits Type Conv 8 rw Res 7:5 ro XOVEN 4 rw Res 3:2 rw En8 1 rw DPMG 0 rw Data Sheet Description Converter mode (only valid in rmii mode) 0 Conv_0, Normal Mode B 1 Conv_1, converter mode ...
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... PHY 10M Module Configuration Register P10_MCR PHY 10M Module Configuration Register Field Bits Type Res 15 ro Data Sheet Offset 11 H Description Reserved Not Applicable 61 ADM7001 Data sheet Registers Description Reset Value 0008 H Rev. 1.07, 2005-09-12 ...
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Field Bits Type SMS 14 rw Res 13 Res 12:11 ITCE 10 Res 9 Res 8:6 Res 5 APD 4 RJM 3 TJD 2 NTH 1 FRL 0 Data Sheet Description 10BASE-T Serial Mode Select. Only available when AD2106 works ...
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... PHY 100M Module Control Register P100_MCR PHY 100M Module Control Register Field Bits Type Res 15:12 ro Res 11:10 rw Res 9:8 FxSel 7 Res 6:5 SCR 4 FEFI 3 CLE 2 ro IAC 1 rw Res 0 Data Sheet Offset 12 H Description Reserved Not Applicable ADMtek reserved bits. ...
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LED Configuration Register LCR LED Configuration Register Field Bits Type Res 15:12 ro LNKCTRL 11:8 ro COLCTRL 7:4 ro Data Sheet Offset 13 H Description Reserved Not Applicable Link/Act LED Control 0000 , Collision B 0001 , All Errors B ...
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Field Bits Type SPDCTRL 3:0 ro Data Sheet Description Speed LED Control 0000 , Collision B 0001 , All Errors B 0010 , Duplex B 0011 , Duplex/Collision B 0100 , Speed B 0101 , Link B 0110 , Transmit ...
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Interrupt Enable Register IER Interrupt Enable Register Field Bits Type Res 15:10 ro XCHG 9 rw SCIE 8 DCIE 7 PRIE 6 LSCE 5 SEIE 4 FCAR 3 TJIE 2 RJIE 1 EESE 0 Data Sheet Offset 14 H Description ...
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... PHY Generic Status Register Note: PHY Status Registers start from ( reserves for further use) PGSR PHY Generic Status Register Field Bits Type Res 15:14 ro Res 13: FXEN 9 XOVER 8 CBLEN 7:0 Data Sheet Offset 16 H Description Reserved Not Applicable Reserved Not Applicable Medium Detect Real Time Status for Medium Detect Signal ...
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... B 1 SPD_1, 100Mb/s B Real Time Link Status 0 LINK_0, Link Down B 1 LINK_1, Link Up B Pause Recommend Value Only Changed when PHY Reset. This bit is disabled automatically when RDUP RPAU_0, Pause Disable B 1 RPAU_1, Pause Enable B 68 ADM7001 Data sheet Registers Description ...
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... RDUP_1, Full Duplex B Speed Recommend Value Only Changed when PHY Reset. 0 RSPD_0, 10M B 1 RSPD_1, 100M B Recommended Auto Negotiation Value Only Changed when PHY Reset. Offset 18 H Description Reserved Not Applicable Auto Negotiation Recommend Value Fiber Select Recommend Value Speed Recommend Value 0 ...
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... ISR Interrupt Status Register Data Sheet Description RMII_SMII Interface 0 RSll_0, Non RMII_SMII Interface B 1 RSll_1, RMII or SMII Interface used B Repeater Mode Recommend Value 0 RM_0, NIC/ RM_1, Repeater B PHY Address Offset ADM7001 Data sheet Registers Description Reset Value 0000 H Rev. 1.07, 2005-09-12 ...
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Field Bits Type Res 15:10 cor XOVC 9 SPDC 8 DUPC 7 PREC 6 LNKC 5 SERR 4 FCAR 3 TJAB 2 RJAB 1 STRE 0 Receive Error Counter Register RECR Receive Error Counter Register Data Sheet Description Reserved Not ...
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Field Bits Type ERB 15:0 ro Chip ID Register CIR Chip ID Register Field Bits Type CHIPID 15:0 ro Data Sheet Description Error Counter Includes. 1 100MFC, 100M False Carrier H 2 100MSE, 100M Symbol Error H 3 10MTJ, 10M ...
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Electrical Characteristics 5.1 DC Characterization 5.1.1 Absolute Maximum Rating Table 23 Absolute Maximum Rating Parameter Symbol V 3.3 V Power Supply CC33 V 2.5 V Power Supply CC25 V Input Voltage IN V Output Voltage OUT T Storage Temperature ...
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AC Characteristics 5.2.1 XI/OSCI (Crystal/Oscillator) Timing (In MII Mode) WB;,B5,6( Figure 25 Crystal/Oscillator Timing Table 26 Crystal/Oscillator Timing Parameter 1) XI/OSCI Clock Period XI/OSCI Clock High XI/OSCI Clock Low XI/OSCI Clock Rise Time, V (max (min.) IL ...
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RMII Timing 5.3.1 REFCLK Input Timing (XI in RMII Mode) t_IN50_RISE Figure 26 REFCLK Input Timing Table 27 REFCLK Input Timing Parameter REFCLK Clock Period REFCLK Clock High REFCLK Clock Low REFCLK Clock Rise Time, V (max ...
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REFCLK Output Timing (CLKO50 in RMII Mode) t_OUT50_RISE Figure 27 REFCLK Output Timing Table 28 REFCLK Output Timing Parameter REFCLK Clock Period REFCLK Clock High REFCLK Clock Low REFCLK Clock Rise Time, V (max (min ...
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WB57B7;(0+ '$7$ 2Q 0HGLXP Figure 28 RMII Transmit Timing Table 29 RMII Transmit Timing Parameter TXD to REFCLK Rising Setup Time TXD to REFCLK Rising Hold Time TXEN asserts to data transmit to medium TXEN asserts to data transmit to ...
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Table 30 RMII Receive Timing Parameter Signal Detected on Medium to CRSDV High Signal Detected on Medium to CRSDV High IDLE Detected on Medium to CRSDV low IDLE Detected on Medium to CRSDV low CRSDV High to Receive Data on ...
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Table 31 REFCLK Input Timing Parameter RXCLK Clock Period(100M) 1) Note RXCLK Clock Period(10M) 2) Note RXCLK Clock High (100M) RXCLK Clock High (10M) RXCLK Clock Low (100M) RXCLK Clock Low (10M) RXCLK Clock Rise Time (max) to ...
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MII Receive Timing Figure 31 MII Receive Timing Table 32 MII Receive Timing Parameter Signal Detected on Medium to CRS High Signal Detected on Medium to CRS High Signal Detected on Medium to RXDV High Signal Detected on Medium ...
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TXCLK Output Timing Figure 32 TXCLK Output Timing Table 33 TXCLK Output Timing Parameter TXCLK Clock Period (100M) TXCLK Clock Period (10M) TXCLK Clock High (100M) TXCLK Clock High (10M) TXCLK Clock Low(100M) TXCLK Clock High (10M) TXCLK Clock ...
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Figure 33 MII Transmit Timing Table 34 MII Transmit Timing Parameter TXD to TXCLK Rising Setup Time TXD to TXCLK Rising Hold Time TXEN asserts to data transmit to medium (100M) TXEN asserts to data transmit to medium (10M) TXEN ...
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Figure 34 GPSI Receive Timing Table 35 GPSI Receive Timing Parameter 10M Receive Clock Period 10M Receive Clock High 10M Receive Clock Low Signal Detected on Medium to CRS High Signal Detected on Medium to Data Valid RXCLK rising to ...
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Table 36 GPSI Transmit Timing Parameter 10M Transmit Clock Period 10M Transmit Clock High 10M Transmit Clock Low TXD to TXCLK Rising Setup Time TXD to TXCLK Rising Hold Time TXEN asserts to data transmit to medium TXEN asserts to ...
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Table 37 Serial Management Interface (MDC/MDIO) Timing (cont’d) Parameter MDC Low MDC to MDIO Delay Time MDIO Input to MDC Setup Time MDIO Input to MDC Hold Time 5.7 Power On Configuration Timing Figure 37 Power On Configuration Timing Table ...
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Packaging ADM7001,Low Profile Quad Flat Package (LQFP) 48 Pin Figure 38 ADM7001,Low Profile Quad Flat Package (LQFP) Data Sheet 86 ADM7001 Data sheet Packaging Rev. 1.07, 2005-09-12 ...
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Table 39 Dimensions for 100 Pin LQFP Package Symbol Millimeter (mm) Min. A – 0.08 1 Θ 0° Θ 0° 1 Θ 11° 2 ...
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Table 39 Dimensions for 100 Pin LQFP Package (cont’d) Symbol Millimeter (mm aaa bbb ccc ddd Data Sheet 0.50 BSC. 5.50 5.50 Tolerance of Form and Position 0.20 0.20 0.08 0.08 88 ADM7001 Data sheet ...
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References [1] [2] [3] [4] [5] [6] Data Sheet 89 ADM7001 Data sheet References Rev. 1.07, 2005-09-12 ...
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Predefined Names Name Data Sheet Note 90 ADM7001 Data sheet Predefined Names Rev. 1.07, 2005-09-12 ...
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Terminology A B Data Sheet 91 ADM7001 Data sheet Terminology Rev. 1.07, 2005-09-12 ...
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Published by Infineon Technologies AG ...