ADM7001XACT1XP Lantiq, ADM7001XACT1XP Datasheet - Page 30

• Manufacturer Part Number: ADM7001XACT1XP
• Manufacturer: Lantiq

Specifications of ADM7001XACT1XP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Automatic “Signal_Detect“ Function Block
When DIS_ANASDEN_N in register 18 is set to 0, ADM7001 doesn't support SDP detection in fiber mode, which
is used to connect to fiber transceiver to indicate there is signal on the fiber. Instead, ADM7001 uses the data on
RXP/RXN to detect consecutive 65 “1” on the receive data (Recovered from RXP/RXN) to determine whether
“Signal” is detected or not. When the detect condition is true (Consecutive 65 bits “1”), internal signal detect signal
will be asserted to inform receive relative blocks to be ready for coming receive activities.
3.1.5
In 100Base FX transmit, the serial data stream is driven out as NRZI PECL signals, which enter fiber transceiver
in differential-pairs form. Fiber transceiver should be available working at 3.3 V environment.
3.1.6
The 10Base-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision,
heartbeat, loopback, jabber, waveshaper, and link integrity functions, as defined in the standard.
provides an overview for the 10Base-T module.
The ADM7001 10Base-T module is comprised of the following functional blocks:
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3.1.7
The ADM7001 10Base-T module is capable of operating in either half-duplex mode or full-duplex mode. In half-
duplex mode, the ADM7001 functions as an IEEE 802.3 compliant transceiver with fully integrated filtering. The
COL signal is asserted during collisions or jabber events, and the CRS signal is asserted during transmitting and
receiving. In full duplex mode the ADM7001 can simultaneously transmit and receive data.
3.1.8
Data encoding and transmission begin when the transmission enable input (TXEN) goes high and continues as
long as the transceiver is in good link state. Transmission ends when the transmission enable input goes low. The
last transition occurs at the center of the bit cell if the last bit is 1, or at the boundary of the bit cell if the last bit is 0.
A differential input receiver circuit accomplishes decoding and a phase-locked loop that separates the
Manchester-encoded data stream into clock signals and NRZ data. The decoder detects the end of a frame when
no more mid bit transitions are detected. Within one and half bit times after the last bit, carrier sense is deasserted.
3.1.9
The ADM7001 integrates all the required signal conditioning functions in its 10Base-T block such that external
filters are not required. Only one isolation transformer and impedance matching resistors are needed for the
10Base-T transmit and receive interface. The internal transmit filtering ensures that all the harmonics in the
transmission signal are attenuated properly.
3.1.10
The smart squelch circuit is responsible for determining when valid data is present on the differential receives. The
ADM7001 implements an intelligent receive squelch on the RXP/RXN differential inputs to ensure that impulse
Data Sheet
Manchester encoder and decoder
Collision detector
Link test function
Transmit driver and receiver
Serial and parallel interface
Jabber and SQE test functions
Polarity detection and correction
100Base-FX Transmitter
10Base-T Module
Operation Modes
Manchester Encoder/Decoder
Transmit Driver and Receiver
Smart Squelch
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Function Description
Rev. 1.07, 2005-09-12
Data sheet
ADM7001
Figure 4