ADM7001XACT1XP Lantiq, ADM7001XACT1XP Datasheet - Page 43

• Manufacturer Part Number: ADM7001XACT1XP
• Manufacturer: Lantiq

Specifications of ADM7001XACT1XP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 17
LNKACT
1
1
0
1
3.4
The SMI consists of two pins, management data clock (MDC) and management data input/output (MDIO). The
ADM7001 is designed to support an MDC frequency specified in the IEEE specification of up to 2.5 MHz. The
MDIO line is bi-directional and may be shared by up to 32 devices.
The MDIO pin requires a 1.5 KΩ pull-up which, during idle and turnaround periods, will pull MDIO to a logic one
state. Each MII management data frame is 64 bits long. The first 32 bits are preamble consisting of 32 contiguous
logic one bits on MDIO and 32 corresponding cycles on MDC. Following preamble is the start-of-frame field
indicated by a <01> pattern. The next field signals the operation code (OP): <10> indicates read from MII
management register operation, and <01> indicates write to MII management register operation. The next two
fields are PHY device address and MII management register address. Both of them are 5 bits wide and the most
significant bit is transferred first.
During Read operation, a 2-bit turn around (TA) time spacing between the register address field and data field is
provided for the MDIO to avoid contention. Following the turnaround time, a 16-bit data stream is read from or
written into the MII management registers of the ADM7001
3.4.1
The ADM7001 supports a preamble suppression mode as indicated by an 1 in bit 6 of the basic mode status
register (Register 1h). If the station management entity (i.e. MAC or other management controller) determines that
all PHYs in the system support preamble suppression by reading a 1 in this bit, then the station management entity
needs not to generate preamble for each management transaction. The ADM7001 requires a single initialization
sequence of 32 bits of preamble following powerup/hardware reset. This requirement is generally met by pulling-
up the resistor of MDIO. While the ADM7001 will respond to management accesses without preamble, a minimum
of one idle bit between management transactions is required as specified in IEEE 802.3u.
When ADM7001 detects that there is physical address match, then it will enable Read/Write capability for external
access. When neither physical address nor register address is matched, then ADM7001 will tristate the MDIO pin.
Figure 21
3.4.2
The ADM7001 can be reset either by hardware or software. A hardware reset is accomplished by applying a
negative pulse, with duration of at least 200 ms to the RC pin of the ADM7001 during normal operation to
Data Sheet
Cable Distance LED Display
Management Register Access
Preamble Suppression
SMII Read Operation
Reset Operation
DUPCOL
1
0
0
1
LEDSPD
0
0
0
1
43
Cable Distance
0 to 40 meters
40 to 80 meters
80 to 120 meters
Reserved
Function Description
Rev. 1.07, 2005-09-12
Data sheet
ADM7001