ADM7001XACT1XP Lantiq, ADM7001XACT1XP Datasheet - Page 50

• Manufacturer Part Number: ADM7001XACT1XP
• Manufacturer: Lantiq

Specifications of ADM7001XACT1XP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Field
PDN
ISO
RAN
DPLX
CT
SSM
Res
Data Sheet
Bits
11
10
9
8
7
6
5:0
Type
rw
rw
rwsc
rw
rw
ro
ro
Description
Power Down Enable
Ored result with PI_PWRDN pin. Setting this bit high or asserting the
PI_PWRDN puts the PHY841F into power down mode. During the power
down mode, TXP/TXN and all LED outputs are tristated and the MII/RMII
interfaces are isolated.
0
1
Isolate PHY841F from Network
Setting this control bit isolates the part from the RMII/MII, with the
exception of the serial management interface. When this bit is asserted,
the PHY841F does not respond to TXD, TXEN and TXER inputs, and it
presents a high impedance on its TXC, RXC, CRSDV, RXER, RXD, COL
and CRS outputs.
0
1
Restart Auto Negotiation
ANEN_RST. Setting this bit while auto negotiation is enabled forces a
new auto negotiation process to start. This bit is self-clearing and returns
to 0 after the auto negotiation process has commenced.
0
1
Duplex Mode
If auto negotiation is disabled, this bit determines the duplex mode for the
link.
0
1
Collision Test
When set, this bit will cause the COL signal of MII interface to be asserted
in response to the assertion of TXEN.
0
1
Speed Selection MSB
SPEED_MSB. Set to 0 all the time indicate that the PHY841F does not
support 1000 Mbit/s function.
Reserved
Not Applicable
B
B
B
B
B
B
B
B
B
B
PDN_0, Normal Operation
PDN_1, Power Down
ISO_0, Normal Operation
ISO_1, Isolate PHY from MII/RMII
RAN_0, Normal Operation
RAN_1, Restart Auto Negotiation Process
DPLX_0, Half Duplex mode
DPLX_1, Full Duplex mode
CT_0, Disable COL signal test
CT_1, Enable COL signal test
50
Registers Description
Rev. 1.07, 2005-09-12
Data sheet
ADM7001