ADM7001XACT1XP Lantiq, ADM7001XACT1XP Datasheet - Page 22

• Manufacturer Part Number: ADM7001XACT1XP
• Manufacturer: Lantiq

Specifications of ADM7001XACT1XP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.2.6
Table 8
Pin or Ball
No.
42
2.2.7
Table 9
Pin or Ball
No.
43
44
19
24
38, 30
Data Sheet
Reset Pin
Reset Pin
Clock Signals, 6 Pins
Clock Signals, 6 pins
Name
MDIO
MDC
Power On
Setting
PHYAD0
MII/RMII/GPSI
Mode
INTR#
PWRDOWN#
TEST[1:0]
Name
RESET#
Pin
Type
I/O
I
I
I
I
Pin
Type
I
Buffer
Type
LVTTL
PU
LVTTL
LVTTL
PU
LVTTL
PU
LVTTL
PD
Buffer
Type
ST
Function
Management Data.
MDIO transfers management data in and out of the device
synchronous to MDC.
Note: LVTTL: Low Voltage TTL Level
Management Data Reference Clock.
A non-continuous clock input for management usage.
ADM7001 will use this clock to sample data input on MDIO and
drive data onto MDIO according to rising edge of this clock.
Note: LVTTL: Low Voltage TTL Level
PHY Address bit 0.
See RXD[3:0] description.
Note: LVTTL: Low Voltage TTL Level
Interrupt
Default active low signal to indicate that there is interrupt event
in SMI register. Active value of interrupt signal can be
configured by register 18.1. Only available when interrupt
mode is selected.
Note: LVTTL: Low Voltage TTL Level
Low Power Operation.
Note: When RESET# is reset to 0 and PWRDOWN# is set to
0
1
Industrial Test Pin.
Keeps low for normal operation.
Note: LVTTL: Low Voltage TTL Level
B
B
Function
Reset Signal
Active low to bring ADM7001 into reset condition.
Recommend keeping low for at least 200 ms to ensure the
stability of the system after power on reset.
22
0, whole ADM7001 blocks will be disabled.
, ADM7001 in low power mode operation. All blocks
except the energy detection and crystal oscillator are de-
activated.
, ADM7001 in normal mode operation.
Note: LVTTL: Low Voltage TTL Level
Interface Description
Rev. 1.07, 2005-09-12
Data sheet
ADM7001