ADM7001XACT1XP Lantiq, ADM7001XACT1XP Datasheet - Page 19

• Manufacturer Part Number: ADM7001XACT1XP
• Manufacturer: Lantiq

Specifications of ADM7001XACT1XP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 7
Pin or Ball
No.
3
45, 46, 47,
48
Data Sheet
MII/RMII/GPSI Interface, 16 pins (cont’d)
Name
Power On
Setting
DIS_AMDIX_EN
MII Mode
RXDV
RMII Mode
CRSDV
GPSI Mode
LOW
Power On
Setting
PHYAD[1:4]
MII Mode
RXD[3:0]
RMII Mode
RXD[1:0]
GPSI Mode
RXD
Pin
Type
I
O
I
O
Buffer
Type
LVTTL
PD
8mA
TTL
PD
8mA
Function
Disable Auto Crossover Function
Value on this pin will be latched by ADM7001 to select Auto
Cross-Over Function.
Note: LVTTL: Low Voltage TTL Level
0
1
MII Receive Data Valid.
Active high signal to indicate that the data on RXD[3:0] is
valid. Synchronous to the rising edge of RXCLK in MII
mode.
RMII Carrier Sense/Receive Data Valid.
Represents Receive Carrier Sense and Data Valid in RMII
mode. CRSDV asserts when the receive medium is non-
idle. The assertion of CRSDV is asynchronous to REFCLK.
At the de-assertion of carrier, CRSDV de-asserts
synchronously to REFCLK only on the first di-bit of RXD. If
there is still data in the FIFO not yet presented onto RXD,
then on the second di-bit of RXD, CRSDV is asserted
synchronously to REFCLK. The toggling of CRSDV_P on
the first and second di-bit continues until all the data in the
FIFO is presented onto RXD. CRSDV is asserted for the
duration of carrier activity for a false carrier event.
Keep Low in GPSI Mode.
PHY Address Select
Value on these 4 pins combined with PHYAD0 will be
stored into ADM7001 as PHY physical address during
power on reset. After power on reset, these 4 pins are
output.
MII Receive Data.
Nibble-wide receive data stream in MII mode. These four
bits are synchronous to the rising edge of RX_CLK and
RXD[3] is the most significant bit.
RMII Receive Data.
RXD0 and RXD1 for the di-bits that are received and are
driven synchronously to REFCLK. RXD[1] is the MSB. Note
that in 100Mb/s mode, RXD can change once per REFCLK
cycle, whereas in 10Mb/s mode, RXD must be held steady
for 10 consecutive REFCLK cycles. RXD[3:2] have not
used in this mode.
GPSI Receive Data.
RXD0 for the designated port inputs the data that is
transmitted and is driven synchronously to RX_CLK in
10Mb/s mode. RXD[3:1] have not used in this mode.
B
B
19
, Enable Auto Crossover
, Disable Auto Crossover
Interface Description
Rev. 1.07, 2005-09-12
Data sheet
ADM7001