ADM7001XACT1XP Lantiq, ADM7001XACT1XP Datasheet - Page 18

• Manufacturer Part Number: ADM7001XACT1XP
• Manufacturer: Lantiq

Specifications of ADM7001XACT1XP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 7
Pin or Ball
No.
4
Data Sheet
MII/RMII/GPSI Interface, 16 pins (cont’d)
Name
Power On
Setting
RMII_EN
MII Mode
RX_CLK
RMII Mode
CLKO50
GPSI Mode
RX_CLK
Pin
Type
I
O
Buffer
Type
LVTTL
PD
16mA
Function
RMII Enable.
Used to select MII or RMII operation. The default value
during power on reset is 0 (Before RMII_EN and GPSI
value is determined)
Note: LVTTL: Low Voltage TTL Level
0
1
MII Receive Clock.
25M Clock output in 100BASE-X mode, 2.5M Clock output
for 10BASE-T MII mode. This clock is recovered from the
received data on the cable input. Due to recovered from
incoming receive data, it is possible that RXCLK starts
running yet RXDV keeps low for a while. During power on
reset, there is no receiving clock driven by ADM7001
RMII 50M Clock Output.
This pin outputs continuous 50M clock in RMII mode. To
reduce the BOM cost for system application, user can
connect this pin directly to REFCLK to proper RMII
operation.
GPSI Receive Clock.
10M clock for 10BASE-T GPSI mode. This clock is
recovered from the received data on the cable input. Due to
recovered from incoming receive data, it is possible that
RXCLK starts running yet CRS keeps low for a while.
During power on reset, there is no receiving clock driven by
ADM7001.
Note: That clock on this pin will not be active during power
B
B
18
, MII Mode
, RMII Mode
on reset due to power on setting.
Interface Description
Rev. 1.07, 2005-09-12
Data sheet
ADM7001