TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 202

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
0x004C
0x000C
0x000A
0x000E
0x0050
0x0060
0x0000
0x0002
0x0004
0x0006
0x0008
Offset
Offset
2 - 0
0
0
3 - 0
0
3 - 0
0
Bits
Bits
DivideClocks
CDR_CS_Setup
PLL_Control
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
AUG1_Mode_Config
XConnectPRBSControl
Table 63: Clock Recovery/Clock Synthesis/SerDes
Name
Name
Table 64: Test Configuration
-
Memory Maps and Bit Descriptions
Init
Init
0x0
0x0
0x0
0x0
0x0
0x0
0x0
rw
rw
rw
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
T_AUG1_Mode_Config
AUG-1 mode configuration for the PRBS generator/analyzer at the
cross connect.
T_XConnectPRBSControl
Configuration of the PRBS generator/analyzer in the cross connect.
Access
Divide clocks by 4.
For every bit in the list, 0x1 divides the corresponding
clock by 4.
•
•
•
Note: The undivided APS receive clock and Transmit
Clock are always 77.76 MHz. Line 1 receive clock fre-
quency depends on the operational mode (77.76 MHz
in STM-4 mode, 19.44 MHz in STM-1 mode.
T_CDR_CS_Setup
Setup and initialization of the Clock Recovery, Serial-
izer and Deserializer (CDR/CS).
T_PLL_Control
Control of the PLL’s in Clock Recovery, Serializer and
Deserializer (CDR/CS).
(T_TestControl)
bit 0: Line 1 receive clock
bit 1: APS receive clock
bit 2: Transmit clock
-
(See page
(See page
(T_ANALOG)
(See page
Description
(See page
Description
177.)
203.)
205.)
205.)
2 0 2 o f 2 26