TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 23

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

2 3 o f 2 2 6
4.3 HIGH ORDER PATH CROSS CONNECT
4.4 TERMINAL SIDE
In the transmit direction, the APS information exchanged between two mate PHAST-12P
devices, including K1/K2 APS signal, signal fail and signal degrade status, is inserted either
from on-chip memory or directly from the TOH monitor.
Finally the serial 622.08 Mbit/s APS port signal is transmitted using the device’s system clock.
The non-blocking high order path cross connect block can connect each output high order
path time slot to each input high order path time slot. The presence of an active cross-
connect does not ‘block’ a cross-connect to another output. AIS or unequipped maintenance
signals can be inserted into each output time slot.
The cross connect has three input buses and three output buses: line side, APS port side and
terminal side. Each bus contains the high order path containers equivalent to an STM-4/
STS-12.
The POH Monitor will terminate all path overhead bytes of the dropped high order path
containers compliant to the latest ITU/ETSI/ANSI standards. Additionally, the received raw
POH overhead bytes are stored in on-chip memory and output on the POH port interface for
external processing (except for BIP where the error mask is calculated). The remote
information, RDI and REI, is output on the external and internal path ring port interfaces for
ring applications.
The high order path payload is subsequently demapped by the ATM/PPP egress block. The
cells or packets are then output on the UTOPIA or POS-PHY interface.
In the transmit direction, ATM cells or PPP packets are input from the UTOPIA or POS-PHY
interface. The ATM/PPP ingress block will map the cells or packets into the high order path
payload.
The POH Generator will optionally insert all path overhead bytes. The POH overhead bytes
can be inserted from on-chip memory or the POH port interface. The remote information, RDI
and REI, can be inserted from the internal or external ring port interface. This selection can
be made on a per high order path basis.
For Test purposes, a PRBS pattern can be generated and inserted on a particular path by the
PHAST-12P. PRBS can be analyzed for bit errors on the receive side.
- Block Diagram Description -
PRELIMINARY TXC-06412B-MB, Ed. 2
PHAST-12P Device
DATA SHEET
TXC-06412B
June 2005