TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 217

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

2 1 7 o f 2 26
Offset
0x000C 11 - 0
0x000A AlarmInhibition
0x0008 AISRDIInsertion
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bits
Summary_Mask
SSF_AIS_Insert_Disable
AIS_AIS_Insert_Disable
EXC_AIS_Insert_Disable
UNEQ_AIS_Insert_Disable
PLM_AIS_Insert_Disable
Reserved
SSF_RDI_Insert_Disable
UNEQ_RDI_Insert_Disable
TIM_RDI_Insert_Disable
PLM_RDI_Insert_Disable
LCD_RDI_Insert_Disable
SSF_UNEQ_Inhibit_Disable
TTIZERO_UNEQ_Contribution_Di
sable
TIM_UNEQ_Contribution_Disable
SSF_EXC_Inhibit_Disable
TIM_EXC_Inhibit_Disable
SSF_DEG_Inhibit_Disable
TIM_DEG_Inhibit_Disable
SSF_RDI_Inhibit_Disable
UNEQ_RDI_Inhibit_Disable
TTIZERO_RDI_Inhibit_Disable
TIM_RDI_Inhibit_Disable
AIS_SSF_Contribution_Disable
TSF_PLM_Inhibit_Disable
Reserved
Reserved
Table 94: POH Monitor Common Configuration
Name
- Memory Maps and Bit Descriptions -
0xFFF Summary mask, one bit per high order path. Least significant bit
Init
0x0 Insertion of AIS on Payload mismatch defect is disabled when 0x1.
0x0 Reserved.
0x0 Insertion of RDI on Loss of cell delineation defect is disabled when
0x0 Inhibition of UNEQ defect by incoming SSF is disabled when 0x1.
0x0 Contribution of TIM to UNEQ defect is disabled when 0x1.
0x0 Inhibition of EXC defect by TIM defect is disabled when 0x1.
0x0 Inhibition of DEG defect by incoming SSF is disabled when 0x1.
0x0 Inhibition of DEG defect by TIM defect is disabled when 0x1.
0x0 Inhibition of RDI defect by TTIZERO defect is disabled when 0x1.
0x0 Inhibition of PLM defect by TSF indication is disabled when 0x1.
0x0 Reserved.
0x0 Reserved.
0x0 Insertion of AIS on incoming Server Signal Fail is disabled when 0x1.
0x0 Insertion of AIS on AIS defect is disabled when 0x1.
0x0 Insertion of AIS on EXC defect is disabled when 0x1.
0x0 Insertion of AIS on unequipped defect is disabled when 0x1.
0x0 Insertion of RDI on incoming Server Signal Fail is disabled when 0x1.
0x0 Insertion of RDI on unequipped defect is disabled when 0x1.
0x0 Insertion of RDI on Trail Trace Identifier Mismatch defect is disabled
0x0 Insertion of RDI on Payload mismatch defect is disabled when 0x1.
0x0 Contribution of TTIZERO to UNEQ defect is disabled when 0x1.
0x0 Inhibition of EXC defect by incoming SSF is disabled when 0x1.
0x0 Inhibition of RDI defect by incoming SSF is disabled when 0x1.
0x0 Inhibition of RDI defect by UNEQ defect is disabled when 0x1.
0x0 Inhibition of RDI defect by TIM defect is disabled when 0x1.
0x0 Contribution of AIS defect to SSF defect is disabled when 0x1.
when 0x1.
0x1.
corresponds to the first high order path.
(T_VCXPM_Common_Config)
Description
PRELIMINARY TXC-06412B-MB, Ed. 2
PHAST-12P Device
DATA SHEET
TXC-06412B
June 2005