TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 210

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
Offset
Offset
0x0000 8 - 0
0x0000
0x0010
0x0020
12.19 EGRESS UTOPIA/POS-PHY LEVEL 2 INTERFACE
10 - 9
13 - 11
14
15
Bits
Bits
SourceTimeslot
SourceBus
Reserved
Force_AIS
Force_Uneq
Common_Config
DirectStatus_Config
PHY_Port_Config
Table 80: Cross Connect Time Slot Configuration
Name
Name
Table 81: UTOPIA/POS-PHY
-
Memory Maps and Bit Descriptions
Init
Init
0x0 Range 0 to 11
0x0 Range 0 to 2
0x0 Reserved.
0x0 The AIS pattern is inserted in this timeslot when 0x1.
0x1 The Uneq pattern is inserted in this timeslot when 0x1.
Source time slot for this output slot.
Source bus for this output slot.
rw
rw
rw
Access
• 0x0 = Line Interface
• 0x1 = APS Interface
• 0x2 = Terminal Interface
(T_DO_UTOPIA_POSPHY)
T_DO_UTOPIA_POSPHY_Common_Config
page
General configuration.
Array (4) of T_DirectStatusTimeslot
Offset between two elements = 0x2.
Array index indicates the CLAV.
Direct status configuration.
Array (12) of T_UTOPIA_POSPHY_PHY_Port_Config
(See page
Offset between two elements = 0x2.
Array index indicates the PHY.
PHY Configuration.
211.)
-
176.)
(T_XConnect_Config)
Description
Description
(See page
2 1 0 o f 2 26
(See
175.)