TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 28

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
APSRXDATAP
APSRXDATAN
APSRXCLK
APSTXDATAN
APSTXDATAP
REFTXCLK1
LINETXCAP
LINETXCLK
Symbol
Symbol
Symbol
Symbol
RECEIVE APS PORT
Lead No. I/O/P
TRANSMIT APS PORT
CLOCK/TIMING INTERFACE
AA6
W9
Y8
Lead No. I/O/P
Lead No.
Lead No.
AA20
AB14
AA7
AB6
Y7
O
I
I/O/P
I
I/O/P
O
O
LVCMOS
LVDS
Type
8mA
LVTTL
Type
LVCMOS
Analog
-
Type
8mA
LVDS
Type
Lead Descriptions
Serial APS Port Receive Data: 622.08 Mbit/s bit-serial data
from mate PHAST-12P.
Receive Divided APS Port Clock: Clock output derived from
the clock recovered from the serial APS port data stream on
APSRXDATAP/N.
The clock rate is programmable to be either 19.44 or 77.76
MHz.
Transmit Reference Clock #1: Reference clock for the
transmit clock synthesizer.
The clock rate is programmable to be either 19.44 or 77.76
MHz. The frequency tolerance for this clock is ± 20 ppm.
The maximum allowed jitter on this clock should be confined
to the same limits as indicated below for the REFTXCLK2P/
REFTXCLK2N leads.
Transmit Divided Clock: Clock output derived from the
synthesized transmit lock.
The clock rate is programmable to be either 19.44 MHz or
77.76 MHz.
Capacitor for the Transmit Line & APS Clock Synthe-
sizer: Optional external capacitor.
Advised capacitor value:
Serial APS Port Transmit Data: 622.08 Mbit/s bit-serial
data to mate PHAST-12P.
Line/Loop - Timing
External Timing
-
Name/Function
Name/Function
Name/Function
Name/Function
STM-1/OC-3
application
1.0 F
N/A
STM-4/OC-12
application
1.0 F
N/A
2 8 o f 2 26