TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 52

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
MPINTR
MPACK
MPD15
MPD14
MPD13
MPD12
MPD10
MPD09
MPD08
MPD07
MPD06
MPD05
MPD04
MPD03
MPD02
MPD01
MPD00
MPSEL
MPD11
MPWR
MPTS
G3
H4
G2
H3
G1
H2
H1
F1
K4
K3
K2
L4
K1
L3
L2
L1
B3
J4
J3
J2
J1
I/O(T)
O(T) LVCMOS
O
I
I
I
LVCMOS
LVCMOS
LVTTL/
LVTTL PHAST-12P Chip Select (Active Low): This active low lead
LVTTL Not Applicable Input: This lead must be tied to VSS.
LVTTL Local Bus Read/Write (Active Low): This active low lead
24mA
8mA
8mA
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Lead Descriptions
Local Data Bus: These leads are the bidirectional data bus
used for transferring data between the PHAST-12P and the
host processor.
MPD15 is the most significant bit.
Motorola MPC8260 Notation: LCL_D[ ]
enables data transfers between the host processor and the
PHAST-12P through a read or write cycle.
Motorola MPC8260 notation: CS
indicates that the actual transfer between the host processor
and the PHAST-12P is a write transfer.
Motorola MPC8260 notation: LWR
Local Bus GPCM Transfer Acknowledge (Active Low): This
lead is used to acknowledge a host processor access. It is syn-
chronous to the MPCLK. To acknowledge an access, MPACK
is asserted during 1 MPCLK cycle and then de-asserted during
3 MPCLK cycles before going in tristate.
For a write access, an acknowledge indicates that data is writ-
ten to the addressed memory location. For a read access, an
acknowledge indicates that the data to be read from the
addressed memory location is available on the data bus.
Motorola MPC8260 notation: LGTA
Interrupt Request (Active low): This lead signals an interrupt
request to the host processor.
Note: MPC8260 Local Bus expects active low interrupt, requir-
ing MPINTLEVEL to be low.
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