PIC24FJ64GA306-I/MR Microchip Technology, PIC24FJ64GA306-I/MR Datasheet - Page 142

• Manufacturer Part Number: PIC24FJ64GA306-I/MR
• Description: 16-bit, 16 MIPS, 64 KB Flash, 8 KB RAM, 53 I/O, LCD, XLP W/Vbat 64 QFN 9x9x0.9mm
• Manufacturer: Microchip Technology

PIC24FJ128GA310 FAMILY
REGISTER 8-44:
DS39996F-page 142
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11-8
bit 7
bit 6-0
R-0, HSC
CPUIRQ
U-0
—
CPUIRQ: Interrupt Request from Interrupt Controller CPU bit
1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU. This happens
0 = No interrupt request is unacknowledged
Unimplemented: Read as ‘0’
VHOLD: Vector Number Capture Configuration bit
1 = The VECNUM bits contain the value of the highest priority pending interrupt
0 = The VECNUM bits contain the value of the last Acknowledged interrupt (i.e., the last interrupt that
Unimplemented: Read as ‘0’
ILR<3:0>: New CPU Interrupt Priority Level bits
1111 = CPU interrupt priority level is 15
•
•
•
0001 = CPU interrupt priority level is 1
0000 = CPU interrupt priority level is 0
Unimplemented: Read as ‘0’
VECNUM<5:0>: Vector Number of Pending Interrupt or Last Acknowledged Interrupt bits
VHOLD = 1: The VECNUM bits indicate the vector number (from 0 to 118) of the last interrupt to occur
VHOLD = 0: The VECNUM bits indicate the vector number (from 0 to 118) of the interrupt request
VECNUM6
R-0, HSC
when the CPU priority is higher than the interrupt priority
has occurred with higher priority than the CPU, even if other interrupts are pending)
U-0
—
INTTREG: INTERRUPT CONTROLLER TEST REGISTER
currently being handled
HSC = Hardware Settable/Clearable bit
W = Writable bit
‘1’ = Bit is set
VECNUM5
R-0, HSC
VHOLD
R/W-0
VECNUM4
R-0, HSC
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
VECNUM3
R-0, HSC
R-0, HSC
ILR3
VECNUM2
R-0, HSC
R-0, HSC
ILR2
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x = Bit is unknown
VECNUM1
R-0, HSC
R-0, HSC
ILR1
VECNUM0
R-0, HSC
R-0, HSC
ILR0
bit 8
bit 0