PIC24FJ64GA306-I/MR Microchip Technology, PIC24FJ64GA306-I/MR Datasheet - Page 205

• Manufacturer Part Number: PIC24FJ64GA306-I/MR
• Description: 16-bit, 16 MIPS, 64 KB Flash, 8 KB RAM, 53 I/O, LCD, XLP W/Vbat 64 QFN 9x9x0.9mm
• Manufacturer: Microchip Technology

14.0
Devices in the PIC24FJ128GA310 family contain
seven independent input capture modules. Each of the
modules offers a wide range of configuration and
operating options for capturing external pulse events
and generating interrupts.
Key features of the input capture module include:
• Hardware configurable for 32-bit operation in all
• Synchronous and Trigger modes of output
• A 4-level FIFO buffer for capturing and holding
• Configurable interrupt generation
• Up to 6 clock sources available for each module,
The module is controlled through two registers:
ICxCON1
A general block diagram of the module is shown in
Figure
FIGURE 14-1:
 2010-2011 Microchip Technology Inc.
Note 1: The ICx inputs must be assigned to an available RPn/RPIn pin before use. See
Note:
modes by cascading two adjacent modules
compare operation, with up to 30 user-selectable
sync/trigger sources available
timer values for several events
driving a separate internal 16-bit counter
Sync and
Trigger Sources
IC Clock
Sources
14-1.
ICX Pin
INPUT CAPTURE WITH
DEDICATED TIMERS
(Register
(PPS)”
Section
Dedicated Timer” (DS39722). The infor-
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F
mation in this data sheet supersedes the
information in the FRM.
(1)
for more information.
14-1) and ICxCON2
ICTSEL<2:0>
34.
Prescaler
Sync and
Family
INPUT CAPTURE BLOCK DIAGRAM
Counter
1:1/4/16
Trigger
Select
Clock
Logic
“Input
Reference
Increment
Reset
Capture
ICM<2:0>
(Register
SYNCSEL<4:0>
Trigger
Clock Synchronizer
Edge Detect Logic
Manual”,
PIC24FJ128GA310 FAMILY
ICXTMR
14-2).
with
and
14.1
14.1.1
When the input capture module operates in a
Free-Running mode, the internal 16-bit counter,
ICxTMR, counts up continuously, wrapping around
from FFFFh to 0000h on each overflow. Its period is
synchronized to the selected external clock source.
When a capture event occurs, the current 16-bit value
of the internal counter is written to the FIFO buffer.
In Synchronous mode, the module begins capturing
events on the ICx pin as soon as its selected clock
source is enabled. Whenever an event occurs on the
selected sync source, the internal counter is reset. In
Trigger mode, the module waits for a Sync event from
another internal module to occur before allowing the
internal counter to run.
Standard, free-running operation is selected by setting
the SYNCSEL bits (ICxCON2<4:0>) to ‘00000’ and
clearing the ICTRIG bit (ICxCON2<7>). Synchronous
and Trigger modes are selected any time the
SYNCSEL bits are set to any value except ‘00000’.
The ICTRIG bit selects either Synchronous or Trigger
mode; setting the bit selects Trigger mode operation. In
both modes, the SYNCSEL bits determine the
sync/trigger source.
When the SYNCSEL bits are set to ‘00000’ and
ICTRIG is set, the module operates in Software Trigger
mode. In this case, capture operations are started by
manually setting the TRIGSTAT bit (ICxCON2<6>).
16
General Operating Modes
SYNCHRONOUS AND TRIGGER
MODES
4-Level FIFO Buffer
ICOV, ICBNE
Event and
ICI1<:0>
Interrupt
ICXBUF
Section 11.4 “Peripheral Pin Select
Logic
Set ICXIF
DS39996F-page 205
16
System Bus
16