PIC24FJ64GA306-I/MR Microchip Technology, PIC24FJ64GA306-I/MR Datasheet - Page 212

• Manufacturer Part Number: PIC24FJ64GA306-I/MR
• Description: 16-bit, 16 MIPS, 64 KB Flash, 8 KB RAM, 53 I/O, LCD, XLP W/Vbat 64 QFN 9x9x0.9mm
• Manufacturer: Microchip Technology

PIC24FJ128GA310 FAMILY
FIGURE 15-1:
15.2
In Compare mode
module can be configured for single-shot or continuous
pulse generation. It can also repeatedly toggle an
output pin on each timer event.
To set up the module for compare operations:
1.
2.
DS39996F-page 212
Note 1: The OCx outputs must be assigned to an available RPn pin before use. See
OC Clock
Sources
Trigger and
Sync Sources
Configure the OCx output for one of the
available Peripheral Pin Select pins.
Calculate the required values for the OCxR and
(for Double Compare modes) OCxRS Duty
Cycle registers:
a)
b)
c)
2: The OCFA/OCFB Fault inputs must be assigned to an available RPn/RPIn pin before use. See
Compare Operations
Determine the instruction clock cycle time.
Take into account the frequency of the
external clock to the timer source (if one is
used) and the timer prescaler settings.
Calculate time to the rising edge of the
output pulse relative to the timer start value
(0000h).
Calculate the time to the falling edge of the
pulse based on the desired pulse width and
the time to the rising edge of the pulse.
(PPS)”
“Peripheral Pin Select (PPS)”
TRIGMODE
SYNCSELx
TRIGSTAT
OCTSELx
OCTRIG
for more information.
(Figure
Trigger and
Sync Logic
OUTPUT COMPARE BLOCK DIAGRAM (16-BIT MODE)
Select
Clock
15-1), the output compare
Increment
Match Event
Reset
Reset
for more information.
Comparator
Comparator
OCxR and
DCB<1:0>
OCxCON1
OCxCON2
OCxTMR
OCxRS
3.
4.
5.
6.
7.
8.
Match Event
Match Event
Write the rising edge value to OCxR and the
falling edge value to OCxRS.
Set the Timer Period register, PRy, to a value
equal to or greater than the value in OCxRS.
Set the OCM<2:0> bits for the appropriate
compare operation (= 0xx).
For Trigger mode operations, set OCTRIG to
enable Trigger mode. Set or clear TRIGMODE
to configure trigger operation and TRIGSTAT to
select a hardware or software trigger. For
Synchronous mode, clear OCTRIG.
Set the SYNCSEL<4:0> bits to configure the
trigger or synchronization source. If free-running
timer operation is required, set the SYNCSEL
bits to ‘00000’ (no sync/trigger source).
Select
OCTSEL<2:0> bits. If necessary, set the TON
bits for the selected timer, which enables the
compare time base to count. Synchronous
mode operation starts as soon as the time base
is enabled; Trigger mode operation starts after a
trigger source event occurs.
the
OC Output and
OCx Interrupt
Fault Logic
Section 11.4 “Peripheral Pin Select
 2010-2011 Microchip Technology Inc.
time
OCMx
OCINV
OCTRIS
FLTOUT
FLTTRIEN
FLTMD
ENFLT<2:0>
OCFLT<2:0>
DCB<1:0>
base
source
Section 11.4
OCFA/OCFB
OCx Pin
with
(1)
the
(2)