PIC24FJ64GA306-I/MR Microchip Technology, PIC24FJ64GA306-I/MR Datasheet - Page 215

• Manufacturer Part Number: PIC24FJ64GA306-I/MR
• Description: 16-bit, 16 MIPS, 64 KB Flash, 8 KB RAM, 53 I/O, LCD, XLP W/Vbat 64 QFN 9x9x0.9mm
• Manufacturer: Microchip Technology

15.3.2
The PWM duty cycle is specified by writing to the
OCxRS and OCxR registers. The OCxRS and OCxR
registers can be written to at any time, but the duty
cycle value is not latched until a match between PRy
and TMRy occurs (i.e., the period is complete). This
provides a double buffer for the PWM duty cycle and is
essential for glitchless PWM operation.
Some important boundary parameters of the PWM duty
cycle include:
EQUATION 15-2:
EXAMPLE 15-1:
TABLE 15-1:
TABLE 15-2:
 2010-2011 Microchip Technology Inc.
Timer Prescaler Ratio
Period Register Value
Resolution (bits)
Note 1:
Timer Prescaler Ratio
Period Register Value
Resolution (bits)
Note 1:
1.
2.
Note 1:
Find the Timer Period register value for a desired PWM frequency of 52.08 kHz, where F
(32 MHz device clock rate) and a Timer2 prescaler setting of 1:1.
Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz
device clock rate:
PWM Frequency
PWM Frequency
T
PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 ms
PWM Period = (PR2 + 1) • T
19.2 ms = PR2 + 1) • 62.5 ns • 1
PR2 = 306
PWM Resolution = log
= (log
= 8.3 bits
CY
Based on F
Based on F
PWM DUTY CYCLE
Note 1: Based on F
Based on T
= 2 * T
10
(16 MHz/52.08 kHz)/log
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (F
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (F
OSC
Maximum PWM Resolution (bits) =
CALCULATION FOR MAXIMUM PWM RESOLUTION
PWM PERIOD AND DUTY CYCLE CALCULATIONS
CY
CY
CY
= 62.5 ns
= F
= F
= 2 * T
OSC
OSC
10
(F
OSC
30.5 Hz
CY
FFFFh
/2; Doze mode and PLL are disabled.
FFFFh
/2; Doze mode and PLL are disabled.
7.6 Hz
CY
16
16
8
8
= F
CY
; Doze mode and PLL are disabled.
/F
PWM
• (Timer2 Prescale Value)
OSC
10
2) bits
/2; Doze mode and PLL are disabled.
)/log
244 Hz
FFFFh
FFFFh
61 Hz
PIC24FJ128GA310 FAMILY
16
16
10
1
1
2) bits
log
10
(
122 Hz
488 Hz
7FFFh
7FFFh
FPWM • (Timer Prescale Value)
15
15
1
1
• If OCxR, OCxRS, and PRy are all loaded with
• If OCxRS is greater than PRy, the pin will remain
See
Table 15-1
4 MIPS and 10 MIPS, respectively.
frequencies and resolutions for a device operating at
0000h, the OCx pin will remain low (0% duty
cycle).
high (100% duty cycle).
Example 15-1
log
3.9 kHz
977 Hz
0FFFh
0FFFh
F
CY
10
12
12
1
1
(2)
and
Table 15-2
15.6 kHz
(1)
3.9 kHz
03FFh
03FFh
(1)
for PWM mode timing details.
10
10
1
1
)
bits
OSC
show example PWM
31.3 kHz
125 kHz
007Fh
007Fh
= 8 MHz with PLL
CY
CY
1
7
1
7
DS39996F-page 215
= 4 MHz)
= 16 MHz)
125 kHz
500 kHz
001Fh
001Fh
(1)
1
5
1
5
(1)