PIC24FJ64GA306-I/MR Microchip Technology, PIC24FJ64GA306-I/MR Datasheet - Page 277

• Manufacturer Part Number: PIC24FJ64GA306-I/MR
• Description: 16-bit, 16 MIPS, 64 KB Flash, 8 KB RAM, 53 I/O, LCD, XLP W/Vbat 64 QFN 9x9x0.9mm
• Manufacturer: Microchip Technology

22.3
22.3.1
REGISTER 22-1:
 2010-2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-8
Note 1:
RTCEN
R/W-0
R/W-0
CAL7
2:
3:
Registers
(2)
The RCFGCAL register is only affected by a POR.
A write to the RTCEN bit is only allowed when RTCWREN = 1.
This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.
RTCC CONTROL REGISTERS
RTCEN: RTCC Enable bit
1 = RTCC module is enabled
0 = RTCC module is disabled
Unimplemented: Read as ‘0’
RTCWREN: RTCC Value Registers Write Enable bit
1 = RTCVALH and RTCVALL registers can be written to by the user
0 = RTCVALH and RTCVALL registers are locked out from being written to by the user
RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple
0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple
HALFSEC: Half Second Status bit
1 = Second half period of a second
0 = First half period of a second
RTCOE: RTCC Output Enable bit
1 = RTCC output is enabled
0 = RTCC output is disabled
RTCPTR<1:0>: RTCC Value Register Window Pointer bits
Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers.
The RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’.
RTCVAL<15:8>:
11 = Reserved
10 = MONTH
01 = WEEKDAY
00 = MINUTES
RTCVAL<7:0>:
11 = YEAR
10 = DAY
01 = HOURS
00 = SECONDS
R/W-0
CAL6
resulting in an invalid data read. If the register is read twice and results in the same data, the data
can be assumed to be valid.
U-0
—
RCFGCAL: RTCC CALIBRATION/CONFIGURATION REGISTER
HSC = Hardware Settable/Clearable bit
W = Writable bit
‘1’ = Bit is set
RTCWREN
R/W-0
R/W-0
CAL5
(2)
RTCSYNC
R-0, HSC
PIC24FJ128GA310 FAMILY
R/W-0
CAL4
(3)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
HALFSEC
R-0, HSC
R/W-0
CAL3
(3)
RTCOE
R/W-0
R/W-0
CAL2
x = Bit is unknown
RTCPTR1
R/W-0
R/W-0
CAL1
(1)
DS39996F-page 277
RTCPTR0
R/W-0
R/W-0
CAL0
bit 8
bit 0