PIC24FJ64GA306-I/MR Microchip Technology, PIC24FJ64GA306-I/MR Datasheet - Page 270

• Manufacturer Part Number: PIC24FJ64GA306-I/MR
• Description: 16-bit, 16 MIPS, 64 KB Flash, 8 KB RAM, 53 I/O, LCD, XLP W/Vbat 64 QFN 9x9x0.9mm
• Manufacturer: Microchip Technology

PIC24FJ128GA310 FAMILY
REGISTER 21-4:
REGISTER 21-5:
DS39996F-page 270
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
S(n+15)Cy
SE(n+15)
S(n+7)Cy
SE(n+7)
R/W-0
R/W-0
R/W-0
R/W-0
For the SEG49 to work correctly, the JTAG needs to be disabled.
SE(n + 15):SE(n): Segment Enable bits
For LCDSE0: n = 0
For LCDSE1: n = 16
For LCDSE2: n = 32
For LCDSE3: n = 48
1 = Segment function of the pin is enabled, digital I/O is disabled
0 = Segment function of the pin is disabled, digital I/O is enabled
S(n + 15)Cy:S(n)Cy: Pixel On bits
For registers, LCDDATA0 through LCDDATA3: n = (16x), y = 0
For registers, LCDDATA4 through LCDDATA7: n = (16(x - 4)), y = 1
For registers, LCDDATA8 through LCDDATA11: n = (16(x - 8)), y = 2
For registers, LCDDATA12 through LCDDATA15: n = (16(x - 12)), y = 3
For registers, LCDDATA16 through LCDDATA19: n = (16(x-16)), y = 4
For registers, LCDDATA20 through LCDDATA23: n = (16(x - 20)), y = 5
For registers, LCDDATA24 through LCDDATA27: n = (16(x - 24)), y = 6
For registers, LCDDATA28 through LCDDATA31: n = (16(x - 28)), y = 7
1 = Pixel is on
0 = Pixel is off
S(n+14)Cy
SE(n+14)
S(n+6)Cy
SE(n+6)
R/W-0
R/W-0
R/W-0
R/W-0
LCDSEx: LCD SEGMENT x ENABLE REGISTER
LCDDATAx: LCD DATA x REGISTER
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
S(n+13)Cy
SE(n+13)
S(n+5)Cy
SE(n+5)
R/W-0
R/W-0
R/W-0
R/W-0
(1)
S(n+12)Cy
SE(n+12)
S(n+4)Cy
SE(n+4)
R/W-0
R/W-0
R/W-0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
S(n+11)Cy
S(n+3)Cy
SE(n+11)
SE(n+3)
R/W-0
R/W-0
R/W-0
R/W-0
S(n+10)Cy
SE(n+10)
S(n+2)Cy
SE(n+2)
R/W-0
R/W-0
R/W-0
R/W-0
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x = Bit is unknown
x = Bit is unknown
S(n+9)Cy
S(n+1)Cy
SE(n+9)
SE(n+1)
R/W-0
R/W-0
R/W-0
R/W-0
S(n+8)Cy
SE(n+8)
S(n)Cy
R/W-0
R/W-0
R/W-0
R/W-0
SE(n)
bit 8
bit 0
bit 8
bit 0