PIC24FJ64GA306-I/MR Microchip Technology, PIC24FJ64GA306-I/MR Datasheet - Page 303

• Manufacturer Part Number: PIC24FJ64GA306-I/MR
• Description: 16-bit, 16 MIPS, 64 KB Flash, 8 KB RAM, 53 I/O, LCD, XLP W/Vbat 64 QFN 9x9x0.9mm
• Manufacturer: Microchip Technology

REGISTER 24-2:
REGISTER 24-3:
 2010-2011 Microchip Technology Inc.
bit 1
bit 0
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-8
bit 7-0
ADCS7
R/W-0
ADRC
R/W-0
These bits are only applicable when the buffer is used in FIFO mode (BUFREGEN = 0). In addition, BUFS
is only used when BUFM = 1.
BUFM: Buffer Fill Mode Select bit
1 = A/D buffer is two, 13-word buffers, starting at ADC1BUF0 and ADC1BUF12, and sequential
0 = A/D buffer is a single, 26-word buffer and fills sequentially from ADC1BUF0 (FIFO mode)
ALTS: Alternate Input Sample Mode Select bit
1 = Uses channel input selects for Sample A on first sample and Sample B on next sample
0 = Always uses channel input selects for Sample A
ADRC: A/D Conversion Clock Source bit
1 = RC Clock
0 = Clock derived from system clock
EXTSAM: Extended Sampling Time bit
1 = A/D is still sampling after SAMP = 0
0 = A/D is finished sampling
PUMPEN: Charge Pump Enable bit
1 = Charge pump for switches is enabled
0 = Charge pump for switches is disabled
SAMC<4:0>: Auto-Sample Time Select bits
11111

00001
00000
ADCS<7:0>: A/D Conversion Clock Select bits
11111111

01000000
00111111 = 64·T

00000001 = 2·T
00000000 = T
EXTSAM
ADCS6
R/W-0
conversions fill the buffers alternately (Split mode)
R-0
AD1CON2: A/D CONTROL REGISTER 2 (CONTINUED)
AD1CON3: A/D CONTROL REGISTER 3
= 31 T
= 1 T
= 0 T
= Reserved
W = Writable bit
‘1’ = Bit is set
CY
PUMPEN
ADCS5
AD
AD
CY
R/W-0
R/W-0
= T
AD
CY
= T
AD
= T
AD
AD
PIC24FJ128GA310 FAMILY
SAMC4
ADCS4
R/W-0
R/W-0
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SAMC3
ADCS3
R/W-0
R/W-0
SAMC2
ADCS2
R/W-0
R/W-0
x = Bit is unknown
SAMC1
ADCS1
R/W-0
R/W-0
DS39996F-page 303
SAMC0
ADCS0
R/W-0
R/W-0
bit 8
bit 0