PIC24FJ64GA306-I/MR Microchip Technology, PIC24FJ64GA306-I/MR Datasheet - Page 336

• Manufacturer Part Number: PIC24FJ64GA306-I/MR
• Description: 16-bit, 16 MIPS, 64 KB Flash, 8 KB RAM, 53 I/O, LCD, XLP W/Vbat 64 QFN 9x9x0.9mm
• Manufacturer: Microchip Technology

PIC24FJ128GA310 FAMILY
REGISTER 29-2:
DS39996F-page 336
bit 23
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 23-16
bit 15
bit 14-13
bit 12-11
bit 10-8
bit 7-6
bit 5
bit 4
FCKSM1
R/PO-1
R/PO-1
IESO
U-1
—
Unimplemented: Read as ‘1’
IESO: Internal External Switchover bit
1 = IESO mode (Two-Speed Start-up) is enabled
0 = IESO mode (Two-Speed Start-up) is disabled
Reserved: Always maintain as ‘1’
ALTVRF<1:0>: Alternate V
00 = Voltage reference input, A/D = RB0/RB1, Comparator = RB0/RB1
01 = Voltage reference input, A/D = RB0/RB1, Comparator = RA9, RA10
10 = Voltage reference input, A/D = RA9/RA10, Comparator = RB0, RB1
11 = Voltage reference input, A/D = RA9/RA10, Comparator = RA9, RA10
FNOSC<2:0>: Initial Oscillator Select bits
111 = Fast RC Oscillator with Postscaler (FRCDIV)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
FCKSM<1:0>: Clock Switching and Fail-Safe Clock Monitor Configuration bits
1x = Clock switching and Fail-Safe Clock Monitor are disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
OSCIOFCN: OSCO Pin Configuration bit
If POSCMD<1:0> = 11 or 00:
1 = OSCO/CLKO/RC15 functions as CLKO (F
0 = OSCO/CLKO/RC15 functions as port I/O (RC15)
If POSCMD<1:0> = 10 or 01:
OSCIOFCN has no effect on OSCO/CLKO/RC15.
IOL1WAY: IOLOCK One-Way Set Enable bit
1 = The IOLOCK bit (OSCCON<6>) can be set once, provided the unlock sequence has been
0 = The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been
FCKSM0
R/PO-1
completed. Once set, the Peripheral Pin Select registers cannot be written to a second time.
completed
U-1
r-1
—
r
CW2: FLASH CONFIGURATION WORD 2
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
OSCIOFCN
R/PO-1
U-1
r-1
—
r
REF
/CV
ALTVRF1
IOL1WAY
R/PO-1
R/PO-1
U-1
REF
—
Pins Selection bits
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ALTVRF0
OSC
R/PO-1
U-1
r-1
—
r
/2)
FNOSC2
R/PO-1
U-1
r-1
—
r
 2010-2011 Microchip Technology Inc.
x = Bit is unknown
POSCMD1
FNOSC1
R/PO-1
R/PO-1
U-1
—
POSCMD0
FNOSC0
R/PO-1
R/PO-1
U-1
—
bit 16
bit 8
bit 0