PIC24FJ64GA306-I/MR Microchip Technology, PIC24FJ64GA306-I/MR Datasheet - Page 95

• Manufacturer Part Number: PIC24FJ64GA306-I/MR
• Description: 16-bit, 16 MIPS, 64 KB Flash, 8 KB RAM, 53 I/O, LCD, XLP W/Vbat 64 QFN 9x9x0.9mm
• Manufacturer: Microchip Technology

8.0
The PIC24F interrupt controller reduces the numerous
peripheral interrupt request signals to a single interrupt
request signal to the PIC24F CPU. It has the following
features:
• Up to 8 processor exceptions and software traps
• Seven user-selectable priority levels
• Interrupt Vector Table (IVT) with up to 118 vectors
• Unique vector for each interrupt or exception
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
• Fixed interrupt entry and return latencies
8.1
The Interrupt Vector Table (IVT) is shown in
The IVT resides in program memory, starting at location,
000004h. The IVT contains 126 vectors, consisting of
8 non-maskable trap vectors, plus up to 118 sources of
interrupt. In general, each interrupt source has its own
vector. Each interrupt vector contains a 24-bit wide
address. The value programmed into each interrupt vec-
tor location is the starting address of the associated
Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority; this is linked to their position in the vector table.
All other things being equal, lower addresses have a
higher natural priority. For example, the interrupt asso-
ciated with Vector 0 will take priority over interrupts at
any other vector address.
PIC24FJ128GA310
non-maskable traps and unique interrupts. These are
summarized in
 2010-2011 Microchip Technology Inc.
Note:
source
support
INTERRUPT CONTROLLER
Interrupt Vector Table
Section 8. “Interrupts” (DS39707). The
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F
information in this data sheet supersedes
the information in the FRM.
Table 8-1
Family
family
and
Table
Reference
devices
8-2.
Figure
implement
Manual”,
PIC24FJ128GA310 FAMILY
8-1.
8.1.1
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in
(INTCON2<15>) control bit provides access to the
AIVT. If the ALTIVT bit is set, all interrupt and exception
processes will use the alternate vectors instead of the
default vectors. The alternate vectors are organized in
the same manner as the default vectors.
The AIVT supports emulation and debugging efforts by
providing a means to switch between an application
and a support environment without requiring the inter-
rupt vectors to be reprogrammed. This feature also
enables switching between applications for evaluation
of different software algorithms at run time. If the AIVT
is not needed, the AIVT should be programmed with
the same addresses used in the IVT.
8.2
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The PIC24F devices clear their registers in response to
a Reset, which forces the PC to zero. The micro-
controller then begins program execution at location,
000000h. The user programs a GOTO instruction at the
Reset address, which redirects program execution to
the appropriate start-up routine.
Note:
Reset Sequence
ALTERNATE INTERRUPT VECTOR
TABLE
Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.
Figure
8-1. The ALTIVT
DS39996F-page 95