ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 102

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 100. HcATLPTDDoneMap register: bit description
Table 101. HcATLPTDSkipMap register: bit description
Table 102. HcATLLastPTD register: bit description
ISP1362_7
Product data sheet
Bit
31 to 0
Bit
31 to 0
Bit
31 to 0
Symbol
PTDDoneBits
[31:0]
Symbol
SkipBits
[31:0]
Symbol
LastPTD
Bits[31:0]
14.9.5 HcATLPTDSkipMap register (R/W: 1Ch/9Ch)
14.9.6 HcATLLastPTD register (R/W: 1Dh/9Dh)
14.9.7 HcATLCurrentActivePTD register (R: 1Eh)
Access
R/W
This is a 32-bit register, and the bit description is given in
represents the first PTD stored in the ATL buffer, bit 1 represents the second PTD stored
in the buffer, and so on. When the bit is set by the HCD, the corresponding PTD is skipped
and is not processed by the host controller. The host controller processes the skipped
PTD only if the HCD has reset its corresponding skipped bit to logic 0. Clearing the
corresponding bit in the HcATLPTDSkipMap register when there is no valid data in the
block will cause unpredictable behavior of the host controller.
Code (Hex): 1C — read
Code (Hex): 9C — write
This is a 32-bit register.
register represents the first PTD stored in the ATL buffer, bit 1 represents the second PTD
stored in the buffer, and so on. The bit that is set to logic 1 by the HCD is used as an
indication to the host controller that its corresponding PTD is the last PTD stored in the
ATL buffer. When the processing of the last PTD is complete, the host controller loops
back to process the first PTD stored in the buffer.
Code (Hex): 1D — read
Code (Hex): 9D — write
This register indicates which PTD stored in the ATL buffer is currently active and is
updated by the host controller. The HCD can use it as a buffer pointer to decide which
PTD locations are currently free to fill in new PTDs to the buffer. This indication helps to
prevent the HCD from accidentally writing into the currently active PTD buffer location.
Table 103
Code (Hex): 1E — read only
Access
R
Access
R/W
Value
0000h
shows the bit allocation of the register.
Value
0000h
Value
0000h
Description
0 — The PTD stored in the ATL buffer was not successfully processed by the
host controller.
1 — The PTD stored in the ATL buffer was successfully processed by the
host controller.
Description
0 — The host controller processes the PTD.
1 — The host controller skips processing the PTD.
Rev. 07 — 29 September 2009
Table 102
Description
0 — The PTD is not the last PTD stored in the buffer.
1 — The PTD is the last PTD stored in the buffer.
gives the bit description of the register. Bit 0 of the
Single-chip USB OTG controller
Table
101. Bit 0 of the register
© ST-ERICSSON 2009. All rights reserved.
ISP1362
102 of 147