ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 96

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 82.
Table 83.
Table 84.
ISP1362_7
Product data sheet
Bit
15 to 0 ISTLBufferSize[15:0] R/W
Bit
15 to 0
Bit
15 to 0
Symbol
Symbol
DataWord[15:0] R/W
HcISTLBufferSize register: bit description
HcISTL0BufferPort register: bit description
HcISTL1BufferPort register: bit description
Symbol
DataWord[15:0]
14.7.2 HcISTL0BufferPort register (R/W: 40h/C0h)
14.7.3 HcISTL1BufferPort register (R/W: 42h/C2h)
Code (Hex): B0 — write
In addition to the HcDirectAddressData register, the ISP1362 provides this register to act
as another data port to access the ISTL0 buffer. The starting address to access the buffer
is always fixed at 0000h. Therefore, random access of the ISTL0 buffer is not allowed.
The bit description of the register is given in
Code (Hex): 40 — read
Code (Hex): C0 — write
The HCD is first required to initialize the HcTransferCounter register with the byte count to
be transferred and check the HcBufferStatus register. The HCD then sends the command
(40h to read from the ISTL0 buffer, and C0h to write to the ISTL0 buffer) to the host
controller through the I/O port of the microprocessor. After the command is sent, the HCD
starts reading data from the ISTL0 buffer or writing data to the ISTL0 buffer. While the
HCD is accessing the buffer, the buffer pointer of ISTL0 also automatically increases.
When the pointer has reached the initialized byte count of the HcTransferCounter register,
the host controller sets the AllEOTInterrupt bit of the HcμPInterrupt register to logic 1 and
updates the HcBufferStatus register.
In addition to the HcDirectAddressData register, the ISP1362 provides this register to act
as another data port to access the ISTL1 buffer. The starting address to access the buffer
is always fixed at 0000h. Therefore, random access of the ISTL1 buffer is not allowed.
The bit description of the register is given in
Code (Hex): 42 — read
Code (Hex): C2 — write
The HCD is first required to initialize the HcTransferCounter register with the byte count to
be transferred and check the HcBufferStatus register. The HCD then sends the command
(42h to read from the ISTL1 buffer, and C2h to write to the ISTL1 buffer) to the host
controller through the I/O port of the microprocessor. After the command is sent, the HCD
starts reading data from the ISTL1 buffer or writing data to the ISTL1 buffer. While the
HCD is accessing the buffer, the buffer pointer of ISTL1 also automatically increases.
Access
Access
R/W
Access
Value
0000h
Value
0000h
Value
0000h
Rev. 07 — 29 September 2009
Description
Data in the ISTL0 buffer to be accessed through this data port.
The size of the buffer to be used for ISO transactions and must be
Description
specified in bytes.
Description
Data in the ISTL1 buffer to be accessed through this data port.
Table
Table
83.
84.
Single-chip USB OTG controller
© ST-ERICSSON 2009. All rights reserved.
ISP1362
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