ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 74

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

ISP1362_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
14.1.6 HcInterruptDisable register (R/W: 05h/85h)
reserved
23
15
7
-
-
-
-
-
-
Table 45.
Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt
bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the
HcInterruptEnable register. Therefore, writing logic 1 to a bit in this register clears the
corresponding bit in the HcInterruptEnable register, whereas writing logic 0 to a bit in this
register leaves the corresponding bit in the HcInterruptEnable register unchanged. On a
read, the current value of the HcInterruptEnable register is returned.
bit allocation of the HcInterruptDisable register.
Code (Hex): 05 — read
Code (Hex): 85 — write
Bit
31
30 to 7
6
5
4
3
2
1
0
RHSC
R/W
22
14
6
0
-
-
-
-
HcInterruptEnable register: bit description
Symbol
MIE
-
RHSC
FNO
UE
RD
SF
-
SO
FNO
R/W
21
13
5
0
-
-
-
-
Rev. 07 — 29 September 2009
Description
MasterInterruptEnable by the HCD: Logic 0 is ignored by the host
controller. Logic 1 enables interrupt generation by events specified in
other bits of this register.
reserved
0 — ignore
1 — enable interrupt generation because of root hub status change
0 — ignore
1 — enable interrupt generation because of frame number overflow
0 — ignore
1 — enable interrupt generation because of unrecoverable error
0 — ignore
1 — enable interrupt generation because of resume detect
0 — ignore
1 — enable interrupt generation because of start-of-frame
reserved
0 — ignore
1 — enable interrupt generation because of scheduling overrun
R/W
UE
20
12
4
0
-
-
-
-
reserved
reserved
R/W
RD
19
11
3
0
-
-
-
-
Single-chip USB OTG controller
R/W
SF
18
10
2
0
-
-
-
-
reserved
Table 46
© ST-ERICSSON 2009. All rights reserved.
17
9
1
-
-
-
-
-
-
ISP1362
provides the
R/W
SO
74 of 147
16
8
0
0
-
-
-
-