ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 37

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

ISP1362_7
Product data sheet
10.5 Power saving in the idle state and during wake-up
10.6 Current capacity of the OTG charge pump
When an interrupt is generated on INT1, perform these steps in the ISR to get the related
OTG status:
The OTG state machine routines are called when any of the inputs is changed. These
inputs come from either OTG registers (hardware) or application program (software). The
outputs of the state machine include control signals to the OTG register (for hardware)
and states or error codes (for software). For more information, refer to ST-Ericsson
document
The ISP1362 can be put in power saving mode if the OTG device is not in a session. This
significantly reduces the power consumption. In this mode, both the peripheral controller
and the host controller are suspended. The PLL and the oscillator are stopped, and the
charge pump is in the suspend state.
As an OTG device, however, the ISP1362 is required to respond to the SRP event. To
support this, a LazyClock is kept running when the chip is in power saving mode. An SRP
event will wake-up the chip (that is, enable the PLL and the oscillator). Besides this, an ID
change or B_SESS_VLD detection can also wake-up the chip. These wake-up events can
be enabled or disabled by programming the related bits of the OtgInterruptEnable register
before putting the chip in power saving mode. If the bit is set, then the corresponding
event (status change) will wake-up the ISP1362. If the bit is cleared, then the
corresponding event will not wake-up the ISP1362.
You can also wake-up the ISP1362 from power saving mode by using the software. This is
accomplished by accessing any of the ISP1362 registers. Accessing a register will assert
CS of the ISP1362, and therefore, set it ‘awake’.
The ISP1362 uses a built-in charge pump to generate a 5 V V
0.3 V voltage source. The only external component required is a capacitor. The value of
this capacitor depends on the amount of current drive required.
recommended capacitor values and the corresponding current drive.
1. Set the polarity and level-triggering or edge-triggering mode of the
2. Set the corresponding bits of the OtgInterruptEnable register (bits 0 to 8, or some of
3. Set bit OTG_IRQ_InterruptEnable of the HcμPInterruptEnable register (bit 9).
4. Set bit InterruptPinEnable of the HcHardwareConfiguration register (bit 0).
1. Read the HcμPInterrupt register. If OTG_IRQ (bit 9) is set, then step 2.
2. Read the OtgInterrupt register. If any of the bits 0 to 4 are set, then step 3.
3. Read the OtgStatus register.
HcHardwareConfiguration register (bits 1 and 2, default is level-triggered, active
LOW).
them).
Ref. 3 “ISP136x Embedded Programming Guide
Rev. 07 — 29 September 2009
Single-chip USB OTG controller
(AN10008)”.
BUS
Table 7
supply from a 3.3 V ±
© ST-ERICSSON 2009. All rights reserved.
provides two
ISP1362
37 of 147