ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 112

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 122. DcDMACounter register: bit allocation
ISP1362_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
15.1.7 DcDMACounter register (R/W: F3h/F2h)
R/W
R/W
15
0
7
0
Table 121. DcDMAConfiguration register: bit description
This command accesses the DcDMACounter register, which consists of two bytes. The bit
allocation is given in
transfer. Reading the register returns the number of remaining bytes in the current
transfer. A bus reset will not change programmed bit values.
The internal DMA counter is automatically reloaded from the DcDMACounter register. For
details, see
Code (Hex): F2/F3 — write or read DcDMACounter register
Transaction — write or read 2 bytes (code or data)
Table 123. DcDMACounter register: bit description
Bit
15
14
13 to 8 -
7 to 4
3
2
1 to 0
Bit
15 to 0
R/W
R/W
14
0
6
0
Symbol
CNTREN
SHORTP
EPDIX[3:0]
DMAEN
-
BURSTL[1:0] Selects the DMA burst length:
Section
Symbol
DMACR[15:0]
R/W
R/W
13
0
5
0
15.1.6.
Table
Rev. 07 — 29 September 2009
Description
Logic 1 enables the generation of an EOT condition, when the
DcDMACounter register reaches zero. Bus reset value: unchanged.
Logic 1 enables short or empty packet mode. When receiving (OUT
endpoint) a short or empty packet, an EOT condition is generated. When
transmitting (IN endpoint), this bit must be cleared. Bus reset value:
unchanged.
reserved
Indicates the destination endpoint for DMA, see
Writing logic 1 enables DMA transfer, logic 0 forces the end of an ongoing
DMA transfer. Reading this bit indicates whether DMA is enabled or not
(0 = DMA stopped; 1 = DMA enabled). This bit is cleared by a bus reset.
reserved
00 — single-cycle mode (1 byte)
01 — burst mode (4 bytes)
10 — burst mode (8 bytes)
11 — burst mode (16 bytes)
Bus reset value: unchanged.
122. Writing to the register sets the number of bytes for a DMA
Description
This field indicates the number of bytes for a DMA transfer.
R/W
R/W
12
0
4
0
DMACR[15:8]
DMACR[7:0]
R/W
R/W
11
0
3
0
Single-chip USB OTG controller
R/W
R/W
10
0
2
0
Table
© ST-ERICSSON 2009. All rights reserved.
R/W
R/W
9
0
1
0
18.
ISP1362
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R/W
R/W
8
0
0
0