ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 71

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 40.
ISP1362_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcCommandStatus register: bit allocation
14.1.3 HcCommandStatus register (R/W: 02h/82h)
31
23
15
7
-
-
-
-
-
-
-
-
The HcCommandStatus register is a 4-byte register, and the bit allocation is given in
Table
HCD, and it also reflects the current status of the host controller. To the HCD, it appears to
be a ‘write to set’ register. The host controller must ensure that bits written as logic 1
become set in the register while bits written as logic 0 remain unchanged in the register.
The HCD may issue multiple distinct commands to the host controller without concern for
corrupting previously issued commands. The HCD has normal read access to all bits.
The SchedulingOverrunCount (SOC) field indicates the number of frames with which the
host controller has detected the scheduling overrun error. This occurs when the periodic
list does not complete before the End-Of-Frame (EOF). When a scheduling overrun error
is detected, the host controller increments the counter and sets the SchedulingOverrun
(SO) field of the HcInterruptStatus register.
Code (Hex): 02 — read
Code (Hex): 82 — write
40. This register is used by the host controller to receive commands issued by the
30
22
14
6
-
-
-
-
-
-
-
-
29
21
13
5
-
-
-
-
-
-
-
-
Rev. 07 — 29 September 2009
reserved
reserved
28
20
12
4
-
-
-
-
-
-
-
-
reserved
reserved
27
19
11
3
-
-
-
-
-
-
-
-
Single-chip USB OTG controller
26
18
10
2
-
-
-
-
-
-
-
-
© ST-ERICSSON 2009. All rights reserved.
25
17
R
0
9
1
-
-
-
-
-
-
ISP1362
SOC[1:0]
HCR
R/W
71 of 147
24
16
R
0
8
0
0
-
-
-
-