ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 90

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 69.
Table 70.
ISP1362_7
Product data sheet
Bit
15 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcTransferCounter register: bit description
HcμPInterrupt register: bit allocation
Symbol
CounterValue[15:0] R/W
14.4.4 HcμPInterrupt register (R/W: 24h/A4h)
INTL_IRQ
R/W
15
7
0
-
-
All the bits in this register are active at power-on reset. None of the active bits, however,
will cause an interrupt on the interrupt pin (INT1), unless they are set by the respective
bits in the HcμPInterruptEnable register and bit 0 of the HcHardwareConfiguration register
is also set.
The bits in this register are cleared only when you write to this register, indicating the bits
to be cleared. To clear all the enabled bits in this register, the HCD must write FFh to this
register.
The bit allocation of the HcμPInterrupt register is given in
Code (Hex): 24 — read
Code (Hex): A4 — write
Table 71.
Bit
15 to 10
9
8
7
6
ClkReady
R/W
14
6
0
-
-
Access Value
Symbol
-
OTG_IRQ
ATL_IRQ
INTL_IRQ
ClkReady
HcμPInterrupt register: bit description
Suspended
0000h
R/W
HC
13
5
0
-
-
Rev. 07 — 29 September 2009
Description
reserved
0 — no event
1 — The OTG interrupt event must read the OtgInterrupt register to get
the cause of the interrupt.
0 — no event
1 — Count value of the HcATLPTDDoneThresholdCount register or the
time-out value of the HcATLPTDDoneThresholdTimeOut register has
reached. The microprocessor is required to read HcATLPTDDoneMap to
check the PTDs that have completed their transactions.
0 — no event
1 — The host controller has detected the last PTD, and there is at least
one interrupt transaction that has received ACK from the device. The
microprocessor is required to read HcINTLPTDDoneMap to check the
PTDs that have received ACK from the device.
0 — no event
1 — The host controller has awakened from the suspend state, and its
internal clock has turned on again.
reserved
OPR_Reg
Description
Number of data bytes to be read from or written to the buffer RAM.
R/W
12
4
0
-
-
Interrupt
AllEOT
R/W
11
3
0
-
-
ISTL1_
Single-chip USB OTG controller
R/W
INT
10
Table
2
0
-
-
70.
OTG_IRQ
ISTL0_
© ST-ERICSSON 2009. All rights reserved.
R/W
R/W
INT
9
0
1
0
ISP1362
SOF_INT
ATL_IRQ
R/W
R/W
90 of 147
8
0
0
0