ISP1362BDTM STEricsson, ISP1362BDTM Datasheet - Page 51

• Manufacturer Part Number: ISP1362BDTM
• Manufacturer: STEricsson

Specifications of ISP1362BDTM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 15.
[1]
[2]
[3]
ISP1362_7
Product data sheet
Endpoint
identifier
0
0
1 to 14
The total amount of the buffer memory storage allocated to enabled endpoints must not exceed 2462 bytes.
IN: input for the USB host (peripheral controller transmits); OUT: output from the USB host (peripheral controller receives).
The data flow direction is determined by the EPDIR bit of the DcEndpointConfiguration register.
Endpoint access and programmability
12.3.1 Endpoints with programmable buffer memory size
12.3.2 Endpoint access
12.3.3 Endpoint buffer memory size
12.3 Endpoint description
Buffer memory size
(bytes)
64 (fixed)
64 (fixed)
programmable
[1]
Remark: If the OneDMA bit in the HcHardwareConfiguration register is set to logic 1,
peripheral controller DMA controller handshake signals DREQ2 and DACK2 are routed to
DREQ1 and DACK1.
When the DMA transfer is terminated, the buffer is also cleared (even if data is not
completely read) and the DMA handler is automatically disabled. For the next DMA
transfer, the DMA controller as well as the DMA handler must be re-enabled.
Each USB device is logically composed of several independent endpoints. An endpoint
acts as a terminus of a communication flow between the USB host and the USB device. At
design time, each endpoint is assigned a unique number (endpoint identifier, see
Table
the endpoint number, and the transfer direction allows each endpoint to be uniquely
referenced.
The peripheral controller has 16 endpoints: endpoint 0 (control IN and OUT) and 14
configurable endpoints, which can individually be defined as interrupt, bulk or
isochronous: IN or OUT. Each enabled endpoint has an associated buffer memory, which
can be accessed either by using programmed I/O interface mode or by using DMA mode.
Table 15
mode access. Endpoints 1 to 14 also support DMA mode access. The peripheral
controller buffer memory DMA access is selected and enabled using bits EPIDX[3:0] and
DMAEN of the DcDMAConfiguration register. A detailed description of the peripheral
controller DMA operation is given in
The size of the buffer memory determines the maximum packet size that the hardware
can support for a given endpoint. Only enabled endpoints are allocated space in the
shared buffer memory storage, disabled endpoints have zero bytes.
programmable buffer memory sizes.
•
•
The DMA count is complete.
DMAEN = 0.
15). The combination of the device address (given by the host during enumeration),
lists the endpoint access modes and programmability. All endpoints support I/O
Double
buffering
no
no
supported
Rev. 07 — 29 September 2009
PIO mode
access
yes
yes
supported
Section
12.4.
DMA mode
access
no
no
supported
Single-chip USB OTG controller
Endpoint type
control OUT
control IN
programmable
© ST-ERICSSON 2009. All rights reserved.
Table 16
ISP1362
[2][3]
[2][3]
lists the
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