NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 102

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

5.1.25
102
PM_CAPID1—Power Management Capabilities (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
31:27
24:22
Bit
Bit
26
25
21
20
19
3
2
1
0
Access &
Access &
Default
Default
000 b
19 h
R/W
R/W
R/W
R/W
0 b
0 b
0 b
0 b
RO
RO
0 b
RO
0 b
RO
RO
0 b
RO
0 b
RO
0 b
VGA Enable (VGAEN)
Controls the routing of CPU initiated transactions targeting VGA compatible I/O and
memory address ranges. See the VGAEN/MDAP table in Device 0, offset 97h[0].
ISA Enable (ISAEN)
Needed to exclude legacy resource decode to route ISA resources to legacy decode
path. Modifies the response by the MCH to an I/O access issued by the CPU that
target ISA I/O addresses. This applies only to I/O addresses that are enabled by the
IOBASE and IOLIMIT registers.
0: All addresses defined by the IOBASE and IOLIMIT for CPU I/O transactions will
1: MCH will not forward to PCI Express link any I/O transactions addressing the last
SERR Enable (SERREN)
0: No forwarding of error messages from secondary side to primary side that could
1: ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result in SERR message
Parity Error Response Enable (PEREN)
Controls whether or not the Master Data Parity Error bit in the Secondary Status
register is set when the MCH receives across the link (upstream) a Read Data
Completion Poisoned TLP
0: Master Data Parity Error bit in Secondary Status register cannot be set.
1: Master Data Parity Error bit in Secondary Status register can be set.
PME Support
This field indicates the power states in which this device may indicate PME wake via
PCI Express messaging. D0, D3hot & D3cold. This device is not required to do
anything to support D3hot & D3cold; it simply must report that those states are
supported. Refer to the PCI Power Management 1.1 specification for encoding
explanation and other power management details.
D2
Hardwired to 0 to indicate that the D2 power management state is NOT supported.
D1
Hardwired to 0 to indicate that the D1 power management state is NOT supported.
Auxiliary Current
Hardwired to 0 to indicate that there are no 3.3Vaux auxiliary current requirements.
Device Specific Initialization (DSI)
Hardwired to 0 to indicate that special initialization of this device is NOT required
before generic class device driver is to use it.
Auxiliary Power Source (APS)
Hardwired to 0.
PME Clock
Hardwired to 0 to indicate this device does NOT support PMEB generation.
be mapped to PCI Express link.
768 bytes in each 1 KB block even if the addresses are within the range defined
by the IOBASE and IOLIMIT registers. Instead of going to PCI Express link these
cycles will be forwarded to DMI where they can be subtractively or positively
claimed by the ISA bridge.
result in an SERR.
when individually enabled by the Root Control register.
1
80h
C8029001h
RO
32 bits
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Host-PCI Express Bridge Registers (D1:F0)