NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 7

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

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Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
8.4
8.5
Functional Description ............................................................................................... 159
9.1
9.2
9.3
9.4
9.5
Electrical Characteristics ............................................................................................ 173
10.1
10.2
10.3
10.4
Ballout and Package Information ................................................................................ 179
11.1
11.2
11.3
8.3.2
8.3.3
8.3.4
Main Memory Address Space (4 GB to Remaplimit) .............................................. 153
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
System Management Mode (SMM) ..................................................................... 155
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.5.8
8.5.9
8.5.10 MCH Decode Rules and Cross-Bridge Address Mapping .............................. 158
8.5.11 Legacy VGA and I/O Range Decode Rules ................................................ 158
Host Interface................................................................................................. 159
9.1.1
9.1.2
9.1.3
9.1.4
System Memory Controller ............................................................................... 160
9.2.1
9.2.2
9.2.3
9.2.4
PCI Express .................................................................................................... 165
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
Power Management ......................................................................................... 172
Clocking......................................................................................................... 172
Absolute Minimum and Maximum Ratings ........................................................... 173
Power Characteristics....................................................................................... 174
Signal Groups ................................................................................................. 175
DC Characteristics ........................................................................................... 177
Ballout ........................................................................................................... 179
MCH Ballout Table ........................................................................................... 182
Package ......................................................................................................... 202
HSEG (FEDA_0000h-FEDB_FFFFh) .......................................................... 153
FSB Interrupt Memory Space (FEE0_0000-FEEF_FFFF) .............................. 153
High BIOS Area.................................................................................... 153
Top of Memory..................................................................................... 153
Memory Re-claim Background ................................................................ 154
Memory Re-mapping............................................................................. 154
PCI Express Configuration Address Space ................................................ 154
PCI Express ......................................................................................... 155
SMM Space Definition ........................................................................... 156
SMM Space Restrictions ........................................................................ 156
SMM Space Combinations ...................................................................... 156
SMM Control Combinations .................................................................... 157
SMM Space Decode and Transaction Handling .......................................... 157
CPU WB Transaction to an Enabled SMM Address Space............................. 157
Memory Shadowing .............................................................................. 157
I/O Address Space................................................................................ 157
PCI Express I/O Address Mapping ........................................................... 158
FSB IOQ Depth .................................................................................... 159
FSB OOQ Depth ................................................................................... 159
FSB GTL+ Termination .......................................................................... 159
FSB Dynamic Bus Inversion ................................................................... 159
System Memory Configuration Registers Overview .................................... 161
DRAM Technologies and Organization...................................................... 162
DRAM Clock Generation......................................................................... 164
DDR2 On Die Terminations .................................................................... 164
PCI Express Architecture ....................................................................... 165
Configurations (Intel® 3010 chipset only) ............................................... 165
Lane Reversal ...................................................................................... 167
PCI Express Straps (Intel® 3010 chipset only) ......................................... 168
Peer-to-Peer ........................................................................................ 169
Peer-to-Peer Latency ............................................................................ 170
PCI Express Error Flow .......................................................................... 171
PCI Express Interrupt and GPE Flow........................................................ 172
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