NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 156

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

8.5.1
8.5.2
8.5.3
Table 8-5.
156
SMM Space Definition
SMM space is defined by its addressed SMM space and its DRAM SMM space. The
addressed SMM space is defined as the range of bus addresses used by the CPU to
access SMM space. DRAM SMM space is defined as the range of physical DRAM memory
locations containing the SMM code. SMM space can be accessed at one of three
transaction address ranges: Compatible, High and TSEG. The Compatible and TSEG
SMM space is not remapped, and therefore the addressed and DRAM SMM space is the
same address range. Since the High SMM space is remapped the addressed and DRAM
SMM space are different address ranges. Note that the High DRAM space is the same as
the Compatible Transaction Address space. The table below describes three unique
address ranges:
SMM Space Restrictions
If any of the following conditions are violated, the results of SMM accesses are
unpredictable and may cause the system to hang:
SMM Space Combinations
When High SMM is enabled (G_SMRAME=1 and H_SMRAM_EN=1), the Compatible
SMM space is effectively disabled. CPU originated accesses to the Compatible SMM
space are forwarded to PCI Express if VGAEN=1 (also depends on MDAP), otherwise
they are forwarded to the DMI. PCI Express and DMI originated accesses are never
allowed to access SMM space.
SMM Space Table
1. The Compatible SMM space must not be set-up as cacheable.
2. High or TSEG SMM transaction address space must not overlap address space
3. Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
4. When TSEG SMM space is enabled, the TSEG space must not be reported to the
• Compatible Transaction Address
• High Transaction Address
• TSEG Transaction Address
Global Enable
G_SMRAME
SMM Space Enabled
assigned to system DRAM, or to any “PCI” devices (including DMI and PCI
Express). This is a BIOS responsibility.
OS as available DRAM. This is a BIOS responsibility.
Compatible (C)
0
1
1
1
1
TSEG (T)
High (H)
H_SMRAM_EN
High Enable
X
0
0
1
1
Transaction Address Space
FEDA_0000h to FEDB_FFFFh
000A_0000h to 000B_FFFFh
(TOLUD-TSEG) to TOLUD
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
TSEG Enable
TSEG_EN
X
0
1
0
1
Compatible (C)
Disabled
Disabled
Disable
Range
Enable
Enable
000A_0000h to 000B_FFFFh
000A_0000h to 000B_FFFFh
(TOLUD-TSEG) to TOLUD
DRAM Space (DRAM)
High (H)
Disable
Disable
Disable
Range
Enable
Enable
System Address Map
TSEG (T)
Disable
Disable
Disable
Range
Enable
Enable