NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 93

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Host-PCI Express Bridge Registers (D1:F0)
5.1.5
5.1.6
5.1.7
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
RID1—Revision Identification (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register contains the revision number of the MCH device 1. These bits are read
only and writes to this register have no effect.
CC1—Class Code (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
This register identifies the basic function of the device, a more specific sub-class, and a
register-specific programming interface.
CL1—Cache Line Size (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
23:16
15:8
7:0
7:0
7:0
Bit
Bit
Bit
Access &
Access &
Access &
Default
Default
Default
06 h
04 h
00 h
00 h
R/W
C0h
RO
RO
RO
RO
Revision Identification Number (RID1)
Indicates the number of times that this device in this component has been
“stepped” through the manufacturing process. It is always the same as the RID
values in all other devices in this component.
Base Class Code (BCC)
Indicates the base class code for this device. This code has the value 06h, indicating
a Bridge device.
Sub-Class Code (SUBCC)
Indicates the sub-class code for this device. The code is 04h indicating a PCI to PCI
Bridge.
Programming Interface (PI)
Indicates the programming interface of this device. This value does not specify a
particular register set layout and provides no practical use for this device.
Cache Line Size (Scratch pad)
Implemented by PCI Express devices as a read-write field for legacy compatibility
purposes but has no impact on any PCI Express device functionality.
1
08h
C0h
RO
8 bits
1
09h
060400h
RO
24 bits
1
0Ch
00h
R/W
8 bits
Description
Description
Description
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