NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 120

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

5.1.55
120
VC1RCTL—VC1 Resource Control (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Controls the resources associated with PCI Express Virtual Channel 1.
30:27
26:24
23:8
7:1
Bit
31
0
Access &
Default
001 b
00 h
R/W
R/W
R/W
0 b
RO
0 b
VC1 Enable
0: Virtual Channel is disabled.
1: Virtual Channel is enabled. See exceptions in note below.
Software must use the VC Negotiation Pending bit to check whether the VC
negotiation is complete. When VC Negotiation Pending bit is cleared, a 1 read from
this VC Enable bit indicates that the VC is enabled (Flow Control Initialization is
completed for the PCI Express port); a 0 read from this bit indicates that the Virtual
Channel is currently disabled.
Notes
To enable a Virtual Channel, the VC Enable bits for that Virtual Channel must be set
in both Components on a Link.
To disable a Virtual Channel, the VC Enable bits for that Virtual Channel must be
cleared in both Components on a Link.
Software must ensure that no traffic is using a Virtual Channel at the time it is
disabled.
Software must fully disable a Virtual Channel in both Components on a Link before
re-enabling the Virtual Channel.
BIOS Requirement: This field must not be set to 1b. VC1 is not a POR feature.
Reserved
VC1 ID
Assigns a VC ID to the VC resource. Assigned value must be non-zero.
This field cannot be modified when the VC is already enabled.
Reserved
TC/VC1 Map
Indicate the TCs (Traffic Classes) that are mapped to the VC resource. Bit locations
within this field correspond to TC values. For example, when bit 7 is set in this field,
TC7 is mapped to this VC resource. When more than one bit in this field is set, it
indicates that multiple TCs are mapped to the VC resource. In order to remove one
or more TCs from the TC/VC Map of an enabled VC, software must ensure that no
new or outstanding transactions with the TC labels are targeted at the given Link.
TC0/VC1 Map
Traffic Class 0 is always routed to VC0.
1
120h
01000000h
RO, R/W
32 bits
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Description
Host-PCI Express Bridge Registers (D1:F0)