NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 159

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

Functional Description
9
9.1
9.1.1
9.1.2
9.1.3
9.1.4
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Functional Description
This chapter describes the MCH interfaces and major functional units.
Host Interface
The cache line size is 64 bytes. Source synchronous transfer is used for the address
and data signals. The address signals are double pumped and a new address can be
generated every other bus clock. At 266 MHz bus clock the address signals run at
533 MT/s. The data is quad pumped and an entire 64 byte cache line can be transferred
in two bus clocks. At 266 MHz bus clock the data signals run at 1066 MT/s for a
maximum bandwidth of 10.7 GB/s.
FSB IOQ Depth
The Scalable Bus supports up to 12 simultaneous outstanding transactions.
FSB OOQ Depth
The MCH supports only one outstanding deferred transaction on the FSB.
FSB GTL+ Termination
The MCH integrates GTL+ termination resistors on die. Also, approximately 2.8 pF
(fast) – 3.3 pF (slow) per pad of on-die capacitance will be implemented to provide
better FSB electrical performance.
FSB Dynamic Bus Inversion
The MCH supports Dynamic Bus Inversion (DBI) when driving and receiving data from
the CPU. DBI limits the number of data signals that are driven to a low voltage on each
quad pumped data phase. This decreases the worst-case power consumption of the
MCH. HDINV[3:0]# indicate if the corresponding 16 bits of data are inverted on the bus
for each quad pumped data phase:
Whenever the CPU or the MCH drives data, each 16-bit segment is analyzed. If more
than 8 of the 16 signals would normally be driven low on the bus the corresponding
HDINV# signal will be asserted and the data will be inverted prior to being driven on
the bus. Whenever the CPU or the MCH receives data it monitors HDINV[3:0]# to
determine if the corresponding data segment should be inverted.
HDINV[3:0]#
HDINV0#
HDINV1#
HDINV2#
HDINV3#
HD[31:16]#
HD[47:32]#
HD[63:48]#
HD[15:0]#
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