NH82801GR S L8FY Intel, NH82801GR S L8FY Datasheet - Page 96

• Manufacturer Part Number: NH82801GR S L8FY
• Manufacturer: Intel

Specifications of NH82801GR S L8FY

• Lead Free Status / RoHS Status: Compliant

5.1.14
96
Only upper 4 bits are programmable. For the purposes of address decode address bits
A [11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range will
be at the top of a 4 KB aligned address block.
SSTS1—Secondary Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
SSTS1 is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side (i.e., PCI Express link side) of the “virtual” PCI-PCI
Bridge embedded within MCH.
10:9
7:4
3:0
4:0
Bit
Bit
15
14
13
12
11
8
7
6
5
Access &
Access &
Default
Default
R/WC
R/WC
R/WC
R/WC
00 b
R/W
0 h
0 b
0 b
0 b
0 b
RO
0 b
RO
RO
0 b
RO
0 b
I/O Address Limit (IOLIMIT)
Corresponds to A[15:12] of the I/O address limit of device 1. Devices between this
upper limit and IOBASE1 will be passed to the PCI Express hierarchy associated
with this device.
Reserved
Detected Parity Error (DPE):
When set indicates that the MCH received across the link (upstream) a Posted Write
Data Poisoned TLP (EP=1)
Received System Error (RSE)
This bit is set when the secondary side sends an ERR_FATAL or ERR_NONFATAL
message due to an error detected by the secondary side, and the SERR Enable bit
in the Bridge Control register is ‘1’.
Received Master Abort (RMA)
This bit is set when the Secondary Side for Type 1 Configuration Space Header
Device (for requests initiated by the Type 1 Header Device itself) receives a
Completion with Unsupported Request Completion Status.
Received Target Abort (RTA)
This bit is set when the Secondary Side for Type 1 Configuration Space Header
Device (for requests initiated by the Type 1 Header Device itself) receives a
Completion with Completer Abort Completion Status.
Signaled Target Abort (STA)
Not Applicable or Implemented. Hardwired to 0. The MCH does not generate Target
Aborts (the MCH will never complete a request using the Completer Abort
Completion status).
DEVSELB Timing (DEVT)
Not Applicable or Implemented. Hardwired to 0.
Reserved
Fast Back-to-Back (FB2B)
Not Applicable or Implemented. Hardwired to 0.
Reserved
66/60 MHz capability (CAP66)
Not Applicable or Implemented. Hardwired to 0.
Reserved
1
1Eh
00h
RO, R/W/C
16 bits
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Host-PCI Express Bridge Registers (D1:F0)